Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 8,564,024 B2
• Filed: 04/09/2009
• Issued: 10/22/2013
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok, Kinzer, Daniel M., Probst, Dean E.
• Primary Examiner(s): Sefer, A.
• Application Number:
  US12/421,448
• Publication Number:
  US 20100140689A1
• Time in Patent Office: 1,657 Days
• Field of Search: 257/170, 257/330, 257/334, 257/213
• US Class Current: 257/213
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a first trench extending into at least a portion of an epitaxial layer of a semiconductor region, the first trench having an end, and a sidewall lined with a dielectric layer, the first trench having a shield electrode disposed in the first trench and having a gate electrode disposed in the first trench, the gate electrode being electrically isolated from the shield electrode of the first trench;

a second trench aligned parallel to the first trench and having an end, the second trench having a gate electrode disposed in the second trench, the gate electrode of the second trench having a width narrower than a width of the gate electrode of the first trench;

a perimeter trench extending into the semiconductor region and having at least a portion aligned perpendicular to the first trench and the second trench, the perimeter trench having a sidewall lined with a dielectric layer and an electrode disposed in the perimeter trench; and

a gap region of the epitaxial layer defining a mesa aligned parallel to the perimeter trench, the gap region being disposed between the portion of the perimeter trench and the end of the first trench and disposed between the portion of the perimeter trench and the end of the second trench.

2. The semiconductor device of claim 1, wherein the electrode disposed in the perimeter trench is electrically coupled to a conductive layer.

3. The semiconductor device of claim 2, further comprising a well region of a first conductivity type disposed in the semiconductor region and in the gap region, the well region is configured to operate at a floating potential.

4. The semiconductor device of claim 1, wherein at least one of the gap region or the electrode disposed in the perimeter trench is configured to operate at a floating potential.

5. The semiconductor device of claim 1, further comprising:

a well region of a first conductivity type disposed in the semiconductor region and in the gap region, the well region is configured to operate at a floating potential.

6. The semiconductor device of claim 1, wherein the portion of the perimeter trench is a first leg of the perimeter trench, the perimeter trench encircles the first trench and the second trench.

7. The semiconductor device of claim 1, wherein the perimeter trench encircles at least 75% of a perimeter around a plurality of trenches including the first trench and the second trench.

8. The semiconductor device of claim 1, wherein the portion of the perimeter trench is a first leg aligned perpendicular to a second leg of the perimeter trench, the second leg is aligned parallel to the first trench.

9. The semiconductor device of claim 8, wherein the first leg and the second leg of the perimeter trench each have an end disposed adjacent to a corner of an array formed by a plurality of trenches including the first trench and the second trench, the end of the first leg and the end of the second leg of the perimeter trench are separated by a gap.

10. The semiconductor device of claim 8, wherein the first leg of the perimeter trench has a different length than the second leg of the perimeter trench.

11. The semiconductor device of claim 1, wherein the gate electrode of the first trench is vertically disposed above the shield electrode.

12. The semiconductor device of the claim 1, wherein a width of the gap region disposed between the perimeter trench and the end of the first trench is greater than a width of the gap region disposed between the perimeter trench and the end of the second trench.

13. A semiconductor device comprising:

a plurality of primary trenches extending into at least a portion of an epitaxial layer of a semiconductor region, the plurality of primary trenches including an inner primary trench disposed between a first outer primary trench and a second outer primary trench, each primary trench from the plurality of primary trenches having an end and a sidewall lined with a dielectric layer, the inner primary trench including a shield electrode, the first outer primary trench including a gate electrode having a width different from a width of a gate electrode included in the inner primary trench;

a perimeter trench extending into the semiconductor region, the perimeter trench having a sidewall lined with a dielectric layer and an electrode disposed in the perimeter trench, the perimeter trench having a first leg aligned parallel to the inner primary trench and a second leg aligned perpendicular to the inner primary trench; and

a gap region of the epitaxial layer defining a mesa aligned parallel to the second leg of the perimeter trench, the gap region being disposed between the second leg of the perimeter trench and the end of each of the plurality of primary trenches.

14. The semiconductor device of claim 13, further comprising a well region of a first conductivity type disposed in the semiconductor region and in the gap region, at least one of the well region or the gap region is configured to operate at a floating potential.

15. The semiconductor device of claim 13, further comprising:

a well region of a first conductivity type disposed in the semiconductor region and in the gap region, the well region is configured to operate at a fixed potential.

16. A semiconductor device comprising:

a plurality of trenches extending into at least a portion of an epitaxial layer of a semiconductor region, each trench from the plurality of trenches having an end, a sidewall lined with a dielectric layer, and a shield electrode disposed therein, the plurality of trenches including a first trench including a gate electrode having a width different than a width of a gate electrode disposed in a second trench included in the plurality of trenches;

a perimeter trench extending into the semiconductor region and having a portion aligned perpendicular to the plurality of trenches, the perimeter trench having a sidewall lined with a dielectric layer and an electrode disposed in the perimeter trench; and

a gap region of the epitaxial layer defining a mesa aligned parallel to the perimeter trench, the gap region being disposed between the perimeter trench and the end of each trench from the plurality of trenches.

17. The semiconductor device of claim 16, wherein the electrode disposed in the perimeter trench is electrically coupled to a conductive layer.

18. The semiconductor device of claim 16, wherein at least one of the gap region or the electrode disposed in the perimeter trench is configured to operate at a floating potential.

19. The semiconductor device of claim 16, wherein the perimeter trench encircles the plurality of trenches.

20. The semiconductor device of claim 16, wherein the portion of the perimeter trench is a first leg of the perimeter trench, the perimeter trench has a second leg aligned perpendicular to the first leg.

21. The semiconductor device of claim 20, wherein the first leg and the second leg of the perimeter trench each have an end disposed adjacent to a corner of an array formed by the plurality of trenches, the end of the first leg and the end of the second leg of the perimeter trench are separated by a gap.

22. The semiconductor device of claim 16, wherein the portion of the perimeter trench is a first leg of the perimeter trench that has a different length than a second leg of the perimeter trench.

23. The semiconductor device of claim 16, wherein each trench from the plurality of trenches has a gate electrode vertically disposed above the shield electrode.