Power semiconductor device with buried source electrode

• US 8,564,051 B2
• Filed: 04/04/2005
• Issued: 10/22/2013
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling
• Primary Examiner(s): MATTHEWS, COLLEEN ANN
• Application Number:
  US11/098,255
• Publication Number:
  US 20050224871A1
• Time in Patent Office: 3,123 Days
• Field of Search: 257/341, 257/401, 257/E21.418, 257/E29.257, 257/E29.118, 257/330
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device that includes a buried source electrode disposed at the bottom of a trench below a respective gate electrode, and a source connector including a finger electrically connecting the buried source to the source contact of the device, and a process for fabricating the device.

Claims

1. A power semiconductor device comprising:

a semiconductor body that includes;

a base region;

a source region disposed on said base region;

at least one high conductivity contact region disposed on said base region;

a common conduction region below said base region;

a plurality of trenches extending through said base region, each trench extending into said semiconductor body from a top surface of said semiconductor body and including a bottom and opposing sidewalls;

a gate electrode disposed inside each trench and insulated from said base region by a respective gate insulation layer, said gate electrode including a bottom surface and a top surface which is below said top surface of said semiconductor body;

an insulation plug residing over a respective top surface of a respective gate electrode and extending above said top surface of said semiconductor body;

a buried source electrode in each trench disposed below and insulated from a respective gate electrode by an insulation interlayer substantially thinner than said insulation plug, said buried source electrode not extending beyond said common conduction region;

at least one source electrode connector;

a source contact electrically coupled to said at least one source electrode connector and extending over said insulation plugs, whereby said source contact is electrically connected to said buried source electrodes; and

an insulation body disposed between said buried source electrodes and said common conduction region.

2. A power semiconductor device according to claim 1, wherein said at least one source electrode connector is adjacent to and insulated from a respective gate electrode.

3. A power semiconductor device according to claim 1, wherein each buried source electrode is insulated from said common conduction region by an insulation body.

4. A power semiconductor device according to claim 3, wherein said insulation body is thicker than said gate insulation layer.

5. A power semiconductor device according to claim 3, wherein said insulation body is comprised of silicon dioxide.

6. A power semiconductor device according to claim 1, wherein said gate insulation layer is comprised of silicon dioxide.

7. A power semiconductor device according to claim 1, wherein said common conduction region and said base region are formed in a silicon body, said silicon body being disposed over a silicon substrate.

8. A power semiconductor device according to claim 7, further comprising a drain contact electrically connected to said substrate.

9. A power semiconductor device according to claim 1, further comprising a gate runner.