Power devices, structures, components, and methods using lateral drift, fixed net charge, and shield

• US 8,564,057 B1
• Filed: 07/13/2010
• Issued: 10/22/2013
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/835,636
• Time in Patent Office: 1,197 Days
• Field of Search: 257/334, 257/270, 257/319, 257/488, 257/329, 257/330, 257/244, 257/355, 438270-271, 438/212
• US Class Current: 257/334
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78624 : the source and the drain regions being asymmetrical
• CPC Class Codes: H03K 17/04106 : in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence

Abstract

Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

Claims

1. A semiconductor device comprising:

an n-type source region;

a p-type body region interposed between said source region and a p-type semiconductor further region;

a gate electrode which is capacitively coupled to controllably invert a portion of said body region, to controllably form therein a channel which connects said source region to said further region;

wherein said further region is laterally interposed between said body region and an n-type drain region;

permanent positive charge, which is embedded in at least one insulating region which adjoins said further region, and which inverts a layer of said further region in proximity to said insulating region;

a shield electrode not overlapping with said gate electrode, which is at least partly interposed between said gate electrode and said drain to reduce capacitive coupling between said gate and said drain; and

a dielectric-filled trench which is within said further region and vertically extends beyond said further region, and which lies at least partly beneath said gate electrode; and

wherein said gate electrode and said shield electrode both have a minimum width which is more than a respective maximum vertical thickness thereof.

2. The semiconductor device of claim 1, wherein said further region is formed as a well.

3. The semiconductor device of claim 1, further comprising a buried region within said further region.

4. The semiconductor device of claim 1, wherein said channel and said further region both carry current flow in a predominantly horizontal plane.

5. The semiconductor device of claim 1, wherein said channel lies in a plane which is predominantly normal to the plane of current flow in said further region.

6. The semiconductor device of claim 1, wherein said channel lies in a plane which is predominantly normal to the surface of a semiconductor die, and said further region carries current flow which is predominantly parallel to said surface.

7. The semiconductor device of claim 1, wherein said gate electrode and said shield electrode are both predominantly planar.

8. The semiconductor device of claim 1, wherein said gate electrode and said shield electrode both lie in the same plane of metallization.

9. The semiconductor device of claim 1, wherein said shield electrode is connected to a fixed potential, but said gate electrode is not.

10. The semiconductor device of claim 1, wherein said further region is part of a semiconductor-on-insulator structure.