Large bit-per-cell three-dimensional mask-programmable read-only memory
First Claim
Patent Images
1. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
- a first memory cell comprising a first resistive layer;
a second memory cell comprising a second resistive layer;
a third memory cell comprising said first and second resistive layers;
wherein each of said first, second and third memory cells comprises a quasi-conduction layer, and said first, second and third memory cells have different current-voltage characteristics.
0 Assignments
0 Petitions
Accused Products
Abstract
A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROMB) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROMB can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.
-
Citations
12 Claims
-
1. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
-
a first memory cell comprising a first resistive layer; a second memory cell comprising a second resistive layer; a third memory cell comprising said first and second resistive layers; wherein each of said first, second and third memory cells comprises a quasi-conduction layer, and said first, second and third memory cells have different current-voltage characteristics. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
-
a first memory cell comprising a first quasi-conduction layer; a second memory cell comprising a second quasi-conduction layer, said second quasi-conductor layer comprising more concentration of at least one resistive element than said first quasi-conductor layer; wherein the memory cells in said memory have N (N>
2) states, and memory cells in different states have different current-voltage characteristics. - View Dependent Claims (9, 10, 11, 12)
-
Specification