Semiconductor substrate, semiconductor device, and manufacturing methods thereof

• US 8,564,134 B2
• Filed: 09/03/2010
• Issued: 10/22/2013
• Est. Priority Date: 02/10/2010
• Status: Expired due to Fees

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Optodevice Company Limited (Seoul Semiconductor Co., Ltd.)
• Inventors: Sakai, Shiro
• Primary Examiner(s): Clark, S. V.
• Assistant Examiner(s): Soderholm, Krista
• Application Number:
  US12/875,649
• Publication Number:
  US 20110193236A1
• Time in Patent Office: 1,145 Days
• Field of Search: 257/773, 257/E23.141, 257/E21.158, 257/E21.09, 257/189
• US Class Current: 257/773
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02656 Special treatments
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a method of manufacturing a gallium nitride (GaN) substrate on a heterogeneous substrate at low cost while realizing performance improvement and long operational lifespan of semiconductor devices, such as LEDs or laser diodes, which are manufactured using the GaN substrate. The semiconductor substrate includes a substrate, a first semiconductor layer arranged on the substrate, a mask arranged on a first region of the first semiconductor layer, a metallic material layer arranged on the first semiconductor layer and the mask, the metallic material layer being arranged in a direction intersecting the mask, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity in the first semiconductor layer and arranged under the metallic material layer.

Claims

1. A semiconductor substrate, comprising:

a substrate;

a first semiconductor layer arranged on the substrate;

a metallic material layer arranged on the first semiconductor layer;

a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer; and

a plurality of cavities in the first semiconductor layer and arranged under the metallic material layer,

wherein the metallic material layer comprises a plurality of stripe-shaped patterns arranged at a constant interval, and

wherein each cavity of the plurality of cavities is arranged under and overlapped with each stripe-shaped pattern of the plurality of stripe-shaped patterns, respectively.

2. The semiconductor substrate of claim 1, further comprising a mask arranged on a first region of the first semiconductor layer,

wherein the metallic material layer is arranged on the mask in a direction intersecting the mask, and

wherein the first region of the first semiconductor layer comprises a portion of a peripheral region on the first semiconductor layer.

3. The semiconductor substrate of claim 1, wherein each stripe-shaped pattern has a constant width.

4. The semiconductor substrate of claim 1, wherein the substrate comprises sapphire or silicon.

16. The semiconductor substrate of claim 2, further comprising a second mask arranged on a second region of the first semiconductor layer,

wherein the metallic material layer is arranged on the second mask, the metallic material layer being arranged in a direction intersecting the second mask.

17. The semiconductor substrate of claim 16, wherein the second region comprises a portion of a peripheral region on the first semiconductor layer.

19. The semiconductor substrate of claim 2, further comprising a granular material comprising a metal from the metallic material layer formed within 200 μ

m of where the metallic material layer and the mask intersect.

20. The semiconductor substrate of claim 19, wherein the granular material comprises a granular mixture of Ga and Ta.

5. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first semiconductor layer on a substrate;

forming a mask on a first region of the first semiconductor layer;

forming a metallic material layer on the first semiconductor layer and the mask, the metallic material layer being formed in a direction intersecting the mask; and

forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a plurality of cavities is formed in the first semiconductor layer and arranged under the metallic material layer,

wherein the metallic material layer comprises a plurality of stripe-shaped patterns arranged at a constant interval, and

wherein each cavity of the plurality of cavities is arranged under and overlapped with each stripe-shaped pattern of the plurality of stripe-shaped patterns, respectively.

6. The method of claim 5, wherein the first region comprises a portion of a peripheral region on the first semiconductor layer.

7. The method of claim 6, wherein each stripe-shaped pattern has a constant width.

8. The method of claim 5, wherein the substrate comprises sapphire or silicon.

11. The method of claim 5, further comprising forming the second semiconductor layer on the mask.

12. The method of claim 5, further comprising a hole formed within 200 μ

m of where the metallic material layer and the mask intersect,

wherein a metal from the metallic material layer evaporates through the hole.

13. The method of claim 5, wherein a granular material comprising a metal from the metallic material layer is formed within 200 μ

m of where the metallic material layer and the mask intersect.

14. The method of claim 5, further comprising separating a first portion of the substrate on which the mask is formed from a second portion of the substrate on which the mask is not formed.

15. The method of claim 5, further comprising separating the substrate from the first semiconductor layer.

18. The method of claim 13, wherein the granular material comprises a granular mixture of Ga and Ta.

9. A semiconductor device, comprising:

a semiconductor substrate, comprising;

a first semiconductor layer arranged on a substrate;

a metallic material layer arranged on the first semiconductor layer;

a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer; and

a plurality of cavities in the first semiconductor layer and arranged under the metallic material layer,

wherein the first region comprises a portion of a peripheral region on the first semiconductor layer,

wherein the metallic material layer comprises a plurality of stripe-shaped patterns arranged at a constant interval, and each stripe-shaped pattern has a constant width,

a first conductive type semiconductor layer arranged on the second semiconductor layer;

an active layer arranged on the first conductive type semiconductor layer; and

a second conductive type semiconductor layer arranged on the active layer,

wherein each cavity of the plurality of cavities is arranged under and overlapped with each stripe-shaped pattern of the plurality of stripe-shaped patterns, respectively.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a semiconductor substrate, comprising;

forming a first semiconductor layer on a substrate;

forming a mask on a first region of the first semiconductor layer;

forming a metallic material layer on the first semiconductor layer and the mask, the metallic material layer being formed in a direction intersecting the mask; and

forming a second semiconductor layer on the first semiconductor layer and the metallic material layer,

wherein a plurality of cavities is formed in the first semiconductor layer and arranged under the metallic material layer,

the first region comprises a portion of a peripheral region on the first semiconductor layer, and

wherein the metallic material layer comprises a plurality of stripe-shaped patterns formed at a constant interval, and each stripe-shaped pattern has a constant width;

forming a first conductive type semiconductor layer on the second semiconductor layer;

forming an active layer on the first conductive type semiconductor layer; and

forming a second conductive type semiconductor layer on the active layer,

wherein each cavity of the plurality of cavities is arranged under and overlapped with each stripe-shaped pattern of the plurality of stripe-shaped patterns, respectively.