Receiver signal probing using a shared probe point

• US 8,564,322 B2
• Filed: 12/21/2009
• Issued: 10/22/2013
• Est. Priority Date: 12/21/2009
• Status: Expired due to Fees

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cases, Moises, Mutnury, Bhyrav M., Pham, Nam H.
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): CLARKE, ADAM S
• Application Number:
  US12/642,914
• Publication Number:
  US 20110149740A1
• Time in Patent Office: 1,401 Days
• Field of Search: 32475401-7621
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/31712 Input or output aspects
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

A device and method are disclosed wherein a receiver signal line within an integrated circuit may be selected for probing. In one embodiment, a plurality of signal pads and a test pad are provided on an external surface of an integrated circuit chip. A plurality of signal lines extends through the integrated circuit chip to the signal pads. A multiplexer on the integrated circuit chip is configured for individually selecting any of the signal lines. An amplifier on the integrated circuit chip amplifies a selected signal and communicates the amplified signal to an externally-accessible test pad to be probed.

Claims

1. An integrated circuit chip, comprising:

a receiver including a plurality of signal lines extending from a plurality of signal pads on an external surface of the integrated circuit chip for receiving a digital signal;

a multiplexer having a plurality of inputs and an output, wherein each input is internally connected to one of the plurality of signal lines on the integrated circuit chip, the multiplexer being changeable between a testing mode and a functional mode, wherein in the testing mode the multiplexer is activated to select any one of the plurality of inputs for probing and communicating the selected input to a single probe point on the external surface of the integrated circuit chip, and in the functional mode the multiplexer disables the single probe point so that none of the signals are communicated to the probe point; and

an amplifier coupled to the multiplexer output for amplifying a signal carried on the selected signal line of the receiver and communicating the amplified signal to the probe point on the external surface of the integrated circuit when in the testing mode.

2. The integrated circuit of claim 1, wherein the plurality of signal pads comprise pads, pins, solder balls, or combinations thereof.

3. The integrated circuit of claim 1, wherein the plurality of signal lines comprise traces, vias, pads, or combinations thereof.

4. The integrated circuit of claim 1, wherein the amplifier is an operational amplifier.

5. The integrated circuit of claim 4, wherein the operational amplifier presents an impedance of between 1 K ohm and 1000 K ohms.

6. A system for testing signals at a receiver within an integrated circuit, comprising:

an integrated circuit chip including a receiver, a multiplexer and an amplifier, wherein the receiver has a plurality of signal lines extending from a plurality of signal pads on an external surface of the integrated circuit chip for receiving a digital signal, wherein the multiplexer has a plurality of inputs each internally connected to one of the plurality of signal lines, wherein the multiplexer is changeable between a testing mode allowing selection of any one of the plurality of inputs for probing and communicating the selected input to a single probe point on the external surface of the integrated circuit chip and a functional mode wherein the multiplexer disables the single probe point so that none of the signals are communicated to the single probe point, and wherein the amplifier is coupled to the multiplexer output for amplifying a signal carried on the selected signal line of the receiver and communicating the amplified signal to a test pad on the external surface of the integrated circuit;

a package substrate having a plurality of signal contacts on a chip side of the package substrate contacting the signal pads on the integrated circuit chip, a test contact on the chip side of the package substrate for contacting the test pad on the supported integrated circuit chip, a plurality of signal conductors extending through the package substrate from the plurality of signal contacts to a board side of the package substrate, and an externally-accessible probe point on the package substrate in communication with the test contact;

a controller coupled through a bus to the multiplexer for selecting one of the plurality of signal lines to test; and

a probe for contacting the externally accessible probe point, wherein the probe communicates with an oscilloscope for analyzing the signal at the externally accessible probe point.

7. The system of claim 6, wherein the bus in an inter-integrated circuit bus.

8. The system of claim 6, further comprising:

a printed circuit board having a physical opening therethrough, wherein the package substrate is secured to the printed circuit board with the externally-accessible probe point on the package substrate accessible through the physical opening.