Semiconductor device

• US 8,564,331 B2
• Filed: 05/02/2012
• Issued: 10/22/2013
• Est. Priority Date: 05/13/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yoneda, Seiichi
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/461,811
• Publication Number:
  US 20120286823A1
• Time in Patent Office: 538 Days
• Field of Search: None
• US Class Current: 326/95
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A semiconductor device in which an input terminal is electrically connected to a first terminal of a first transmission gate; a second terminal of the first transmission gate is electrically connected to a first terminal of a first inverter and a second terminal of a functional circuit; a second terminal of the first inverter and a first terminal of the functional circuit are electrically connected to a first terminal of a second transmission gate; a second terminal of the second transmission gate is electrically connected to a first terminal of a second inverter and a second terminal of a clocked inverter; a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to an output terminal; and the functional circuit includes a data holding portion between a transistor with small off-state current and a capacitor.

Claims

1. A semiconductor device comprising:

a circuit, the circuit comprising an input terminal, a first transmission gate, a second transmission gate, a first inverter, a second inverter, a functional circuit, a clocked inverter, and an output terminal,

the functional circuit comprising;

a first transistor, a second transistor, a third transistor, and a capacitor,

wherein the first transistor and the second transistor are p-channel transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the capacitor, and

wherein the other of the electrodes of the capacitor is electrically connected to a second wiring,

wherein the input terminal is electrically connected to a first terminal of the first transmission gate,

wherein a second terminal of the first transmission gate is electrically connected to a first terminal of the first inverter and the other of the source and the drain of the second transistor,

wherein a second terminal of the first inverter and a gate of the second transistor are electrically connected to a first terminal of the second transmission gate,

wherein a second terminal of the second transmission gate is electrically connected to a first terminal of the second inverter and a second terminal of the clocked inverter, and

wherein a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to the output terminal.

2. The semiconductor device according to claim 1,

wherein the first wiring and the second wiring are each a power supply potential line supplied with a constant potential, and

wherein a potential supplied to the first wiring is higher than a potential supplied to the second wiring.

3. The semiconductor device according to claim 1,

wherein a gate of the first transistor is supplied with a timing signal which is set to a high level or a low level,

wherein the clocked inverter is configured to be supplied with a clock signal,

wherein before the circuit is switched to an off state, the third transistor is turned off,

wherein when the circuit is switched to an on state after the circuit is switched to the off state, the clock signal is not input to the clocked inverter and a wiring to which the clock signal is input is held at a constant potential,

wherein after the circuit is switched to the on state, the timing signal is set to the high level and then, the third transistor is turned on, and

wherein after the third transistor is turned on, a same signal as the clock signal is input as the timing signal.

4. The semiconductor device according to claim 1, wherein an off-state current per micrometer of unit channel width of the third transistor is smaller than or equal to 10 aA at room temperature.

5. The semiconductor device according to claim 1, wherein the third transistor comprises an oxide semiconductor layer.

6. The semiconductor device according to claim 5, wherein the oxide semiconductor layer includes crystal.

7. A semiconductor device comprising:

a circuit, the circuit comprising an input terminal, a first transmission gate, a second transmission gate, a first inverter, a second inverter, a functional circuit, a clocked inverter, and an output terminal,

the functional circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor,

wherein the first transistor and the second transistor are p-channel transistors,

wherein a node is electrically connected to one of a source and a drain of the fourth transistor via the third transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the capacitor, and

wherein the other of the electrodes of the capacitor is electrically connected to a second wiring,

wherein the input terminal is electrically connected to a first terminal of the first transmission gate,

wherein a second terminal of the first transmission gate is electrically connected to a first terminal of the first inverter and the other of the source and the drain of the second transistor,

wherein a second terminal of the first inverter and a gate of the second transistor are electrically connected to a first terminal of the second transmission gate,

wherein a second terminal of the second transmission gate is electrically connected to a first terminal of the second inverter and a second terminal of the clocked inverter, and

wherein a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to the output terminal.

8. The semiconductor device according to claim 7, wherein a gate of the fourth transistor is configured to be supplied with a reset signal.

9. The semiconductor device according to claim 7,

wherein the first wiring and the second wiring are each a power supply potential line supplied with a constant potential, and

wherein a potential supplied to the first wiring is higher than a potential supplied to the second wiring.

10. The semiconductor device according to claim 7,

wherein a gate of the first transistor is supplied with a timing signal which is set to a high level or a low level,

wherein the clocked inverter is configured to be supplied with a clock signal,

wherein before the circuit is switched to an off state, the third transistor is turned off,

wherein when the circuit is switched to an on state after the circuit is switched to the off state, the clock signal is not input to the clocked inverter and a wiring to which the clock signal is input is held at a constant potential,

wherein after the circuit is switched to the on state, the timing signal is set to the high level and then, the third transistor is turned on, and

wherein after the third transistor is turned on, a same signal as the clock signal is input as the timing signal.

11. The semiconductor device according to claim 7, wherein an off-state current per micrometer of unit channel width of the third transistor is smaller than or equal to 10 aA at room temperature.

12. The semiconductor device according to claim 7, wherein the third transistor comprises an oxide semiconductor layer.

13. The semiconductor device according to claim 12, wherein the oxide semiconductor layer includes crystal.

14. A semiconductor device comprising:

a flip-flop circuit comprising an inverter and a functional circuit,

wherein the functional circuit comprising a first transistor, a second transistor comprising an oxide semiconductor layer and a capacitor,

wherein the first transistor is a p-channel transistor,

wherein the first transistor comprises a single crystal semiconductor layer,

wherein one of a source and a drain of the first transistor is electrically connected to a first terminal of the inverter and one of a source and a drain of the second transistor,

wherein a gate of the first transistor is electrically connected to a second terminal of the inverter, and

wherein one of electrodes of the capacitor is electrically connected to the other of a source or a drain of the transistor.

15. The semiconductor device according to claim 14, wherein an off-state current per micrometer of unit channel width of the second transistor is smaller than or equal to 10 aA at room temperature.

16. The semiconductor device according to claim 14, wherein the oxide semiconductor layer includes crystal.

17. A semiconductor device comprising:

a circuit, the circuit comprising a first transistor, a second transistor, a third transistor, and a capacitor,

wherein the first transistor and the second transistor are p-channel transistors,

wherein the third transistor comprises an oxide semiconductor layer,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the capacitor, and

wherein the other of the electrodes of the capacitor is electrically connected to a second wiring.

18. The semiconductor device according to claim 17,

wherein the circuit further comprises a fourth transistor,

wherein a node is electrically connected to one of a source and a drain of the fourth transistor via the third transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wiring, and

wherein a gate of the fourth transistor is configured to be supplied with a reset signal.

19. The semiconductor device according to claim 17,

wherein the first wiring and the second wiring are each a power supply potential line supplied with a constant potential, and

wherein a potential supplied to the first wiring is higher than a potential supplied to the second wiring.

20. The semiconductor device according to claim 17, wherein an off-state current per micrometer of unit channel width of the third transistor is smaller than or equal to 10 aA at room temperature.

21. The semiconductor device according to claim 17, wherein the oxide semiconductor layer includes crystal.