Shift register and liquid crystal display having the same

• US 8,564,523 B2
• Filed: 03/23/2006
• Issued: 10/22/2013
• Est. Priority Date: 09/05/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Moon, Seung-Hwan
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): Tung, David
• Application Number:
  US11/387,261
• Publication Number:
  US 20060164376A1
• Time in Patent Office: 2,770 Days
• Field of Search: 345/87, 345 94- 96, 345 98-100
• US Class Current: 345/100
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a shift register and an LCD having the same, the shift register includes plural stages having odd stages for receiving a first clock signal and a first control signal and even stages for receiving a second clock signal and a second control signal. Each of the plural stages includes a pull-up section for providing one of first and second clock signals to an output terminal, a pull-down section for providing a first power voltage to the output terminal, a pull-up driving section for turning on/off the pull-up section in response to an output signal of a front stage and turning off the pull-up section in response to the first and second control signals, a first pull-down driving section for outputting a third control signal, and a second pull-down driving section for turning off the pull-down section in response to the input signal and turning on the pull-down section in response to the third control signal.

Claims

1. A shift register including a plurality of stages, each of the plurality of stages receiving at least one of a plurality of clock signals and a plurality of control signals,

each of the plurality of stages comprising:

a pull-up section to output the received one of the plurality of clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a first one of the plurality of control signals and to turn off the pull-up section in response to a second one of the plurality of control signals;

a pull-down section to output a first power voltage to the output terminal;

a first pull-down driving section to output a third control signal based on turn-on and turn-off of the pull-up section; and

a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section,

wherein the first pull-down driving section includes a first transistor and a second transistor in series,

wherein the second pull-down driving section includes a first transistor and a second transistor in series,

wherein the first power voltage is applied to an end portion of the first transistor of the first pull-down driving section and an end portion of the first transistor of the second pull-down driving section,

wherein a second power voltage is applied to an end portion of the second transistor of the first pull-down driving section and an end portion of the second transistor of the second pull-down driving section, and

wherein a current electrode of the first transistor of the first pull-down driving section is connected to a control electrode of the first transistor of the second pull-down driving section to output the third control signal.

2. The shift register of claim 1, wherein the second pull-down driving section turns off the pull-down section in response to an input signal on an input node of the pull-up section.

3. The shift register of claim 1, wherein the pull-up driving section comprises:

a capacitor connected between an input node of the pull-up section and the output terminal;

a first transistor of which a first current electrode is coupled to the second power voltage, a control electrode is coupled to the input terminal, and a second current electrode is coupled to the input node of the pull-up section;

a second transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an input node of the pull-down section and a second current electrode is coupled to the first power voltage; and

a third transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an output terminal of one of next successive stages and a second current electrode is coupled to the first power voltage.

4. The shift register of claim 1, wherein the

first transistor of the second pull down driving section includes a first current electrode coupled to the second power voltage, the control electrode and a second current electrode coupled to an input node of the pull-down section, and

the second transistor of the second pull down driving section includes a first current electrode coupled to the input node of the pull-down section, a control electrode coupled to an input node of the pull-up section and a second current electrode coupled to the first power voltage.

5. The shift register of claim 4, wherein a channel width ratio of the first transistor of the second pull down driving section to the second transistor of the second pull down driving section is substantially 1:

1.

6. The shift register of claim 1, wherein the

first transistor of the first pull down driving section includes a first current electrode and a control electrode commonly coupled to the second power voltage, and

the second transistor of the first pull down driving section includes a first current electrode coupled to a current electrode of the first transistor whereat the third control signal is produced, a control electrode coupled to an input node of the pull-up section, and a second current electrode coupled to the first power voltage.

7. The shift register of claim 6, wherein a channel width ratio of the first transistor of the first pull down driving section to the second transistor of the first pull down driving section is substantially 1:

1.

8. The shift register of claim 1, wherein the plurality of clock signals include a first clock signal and a second clock signal having a phase opposite to a phase of the first clock signal, and wherein

odd numbered stages respectively receive the first clock signal and

even numbered stages respectively receive the second clock signal.

9. The shift register of claim 1, wherein an output of the pull-up driving section is coupled to an input node of the pull-up section.

10. The shift register of claim 1, wherein the second pull-down driving section is coupled to an input node of the pull-down section.

11. The shift register of claim 1, wherein the first pull-down driving section is coupled to an input node of the pull-up section.

12. The display device of claim 11, wherein the first pull-down driving section is coupled to an input node of the pull-up section and the second pull-down driving section is coupled to an input node of the pull-down section.

13. The shift register of claim 1, wherein the stages are connected one after another to each other.

14. The shift register of claim 1, wherein the pull-down section is turned on when the first transistor of the second pull-down driving section is turned on.

15. The shift register of claim 1, wherein the first power voltage is a DC voltage, and the second power voltage is a DC voltage.

16. A display device comprising a display cell array circuit, a scan driving circuit formed on a substrate, the display cell array circuit comprising a plurality of data lines and a plurality of gate lines, each of the display cell arrays coupled to a corresponding pair of a data line and a gate line, the scan driving circuit comprising a shift register including a plurality of stages, each of the plurality of stages receiving one of a plurality of clock signals and a plurality of control signals, each of the plurality of stages comprising:

a pull-up section to output the received one of the plurality of the clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a first one of the plurality of control signals and turn off the pull-up section in response to a second one of the plurality of control signals;

a pull-down section to output a first power voltage to the output terminal;

a first pull-down driving section to output a third control signal based on turn-on and turn-off of the pull-up section; and

a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section,

wherein the first pull-down driving section includes a first transistor and a second transistor in series,

wherein the second pull-down driving section includes a first transistor and a second transistor in series,

wherein the first power voltage is applied to an end portion of the first transistor of the first pull-down driving section and an end portion of the first transistor of the second pull-down driving section,

wherein a second power voltage is applied to an end portion of the second transistor of the first pull-down driving section and an end portion of the second transistor of the second pull-down driving section, and

wherein a current electrode of the first transistor of the first pull-down driving section is connected to a control electrode of the first transistor of the second pull-down driving section to output the third control signal.

17. The display device of claim 16, wherein the second pull-down driving section turns off the pull-down section in response to an input signal on an input node of the pull-up section.

18. The display device of claim 16, wherein the plurality of clock signals include a first clock signal and a second clock signal having a phase opposite to a phase of the first clock signal, and wherein

odd numbered stages respectively receive the first clock signal and

even numbered stages respectively receive the second clock signal.

19. The display device of claim 16, wherein the stages are connected one after another to each other.

20. The display device of claim 16, wherein the pull-down section is turned on when the first transistor of the second pull-down driving section is turned on.

21. The display device of claim 16, wherein the first power voltage is a DC voltage.

22. A scan driver including a shift register, the shift register sequentially outputting output signals of each of the stages, each of the stages receiving at least one of a plurality of clock signals and one of a plurality of control signals, each of the plurality of stages comprising:

a pull-up section to output the received one of the plurality of clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a first one of the control signals and to turn off the pull-up section in response to a second one of the plurality of control signals;

a pull-down section to output a first power voltage to the output terminal;

a first pull-down driving section to output a third control signal based on turn-on and turn-off of the pull-up section; and

a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section,

wherein the second pull-down driving section includes a pair of transistors in series having a channel length ratio of substantially 1;

2 and a channel width ratio of substantially 1;

1,

wherein the pull-up driving section comprises;

a capacitor connected between an input node of the pull-up section and the output terminal;

a first transistor of which a first current electrode is coupled to a second power voltage, a control electrode coupled to the input terminal, and a second current electrode is coupled to the input node of the pull-up section;

a second transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an input node of the pull-down section and a second current electrode is coupled to the first power voltage; and

a third transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an output terminal of one of next successive stages and a second current electrode is coupled to the first power voltage.

23. The scan driver of claim 22, wherein the plurality of clock signals includes a first clock signal and a second clock signal having a phase opposite to a phase of the first clock signal, and wherein

odd numbered stages respectively receive the first clock signal and

even numbered stages respectively receive the second clock signal.

24. The scan driver of claim 22, wherein with respect to a first transistor of the pair, a first current electrode thereof is coupled to a second power voltage node, a control electrode thereof is coupled to the third control signal of the first pull-down driving section and a second current electrode thereof is coupled to an input node of the pull-down section, and

wherein with respect to a second transistor of the pair, a first current electrode thereof is coupled to the input node of the pull-down section, a control electrode thereof is coupled to an input node of the pull-up section and a second current electrode thereof is coupled to the first power voltage.

25. The scan driver of claim 22, wherein the first pull-down driving section comprises:

a third transistor of which a first current electrode and a control electrode are commonly coupled to a second power voltage;

a fourth transistor of which a first current electrode is coupled to a second electrode of the third transistor whereat the third control signal is output, a control electrode is coupled to the input node of the pull-up section, and a second current electrode is coupled to the first power voltage node.

26. The scan driver of claim 22, wherein the stages are connected one after another to each other.

27. The scan driver of claim 22, wherein the pull-down section is turned on when a first transistor of the second pull-down driving section is turned on.

28. The scan driver of claim 22, wherein the first power voltage is a DC voltage.

29. A shift register in which a plurality of stages are connected one after another to each other, each of the plurality of stages receiving at least one of a plurality of clock signals and a plurality of control signals

each of the plurality of stages comprising:

a pull-up section to output the received one of the plurality of clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a first one of the plurality of control signals and to turn off the pull-up section in response to a second one of the plurality of control signals;

a pull-down section to output a first power voltage to the output terminal;

a first pull-down driving section to output a third control signal based on turn-on and turn-off of the pull-up section; and

a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section,

wherein the pull-up driving section comprises;

a capacitor connected between an input node of the pull-up section and the output terminal;

a first transistor of which a first current electrode is coupled to a second power voltage, a control electrode is coupled to the input terminal, and a second current electrode is coupled to the input node of the pull-up section;

a second transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an input node of the pull-down section and a second current electrode is coupled to the first power voltage; and

a third transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an output terminal of one of next successive stages and a second current electrode is coupled to the first power voltage.

30. A display device comprising a display cell array circuit, a scan driving circuit formed on a substrate, the display cell array circuit comprising a plurality of data lines and a plurality of gate lines, each of the display cell arrays coupled to a corresponding pair of a data line and a gate line, the scan driving circuit comprising a shift register including a plurality of stages, each of the plurality of stages receiving one of a plurality of clock signals and a plurality of control signals, each of the plurality of stages comprising:

a pull-up section to output the received one of the plurality of the clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a first one of the plurality of control signals and turn off the pull-up section in response to a second one of the plurality of control signals;

a pull-down section to output a first power voltage to the output terminal;

a first pull-down driving section to output a third control signal when the first power voltage is outputted at the output terminal; and

a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section,

wherein the first pull-down driving section includes a first transistor and a second transistor in series,

wherein the second pull-down driving section includes a first transistor and a second transistor in series,

wherein the first power voltage is applied to an end portion of the first transistor of the first pull-down driving section and an end portion of the first transistor of the second pull-down driving section,

wherein a second power voltage is applied to an end portion of the second transistor of the first pull-down driving section and an end portion of the second transistor of the second pull-down driving section, and

wherein a current electrode of the first transistor of the first pull-down driving section is connected to a control electrode of the first transistor of the second pull-down driving section to output the third control signal.