Method of implementing an accelerated graphics port for a multiple memory controller computer system

• US 8,564,602 B2
• Filed: 07/22/2010
• Issued: 10/22/2013
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph
• Primary Examiner(s): Chauhan, Ulka
• Assistant Examiner(s): Valdez, Patrick F
• Application Number:
  US12/841,376
• Publication Number:
  US 20110032261A1
• Time in Patent Office: 1,188 Days
• Field of Search: 345/532, 345/503, 345/519, 345/536, 345/541, 345/543, 345/568
• US Class Current: 345/532
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.

Claims

1. A method of manufacturing a multiple memory controller computer comprising:

providing a first memory controller and a second memory controller for controlling a main memory, wherein each memory controller comprises a configuration register that defines a range of addresses for accelerated graphic transactions, the first memory controller being connected to the second memory controller and a central processing unit via a bus, wherein the bus is separate from a chipset of each of the memory controllers, and each memory controller is independent of the central processing unit;

connecting the first memory controller to an accelerated graphics processor via a point-to-point connection that bypasses the bus;

providing an address remapping table of entries in the main memory, wherein the address remapping table is located in the range of addresses for the accelerated graphic transactions; and

when a memory transaction is associated with graphics data, translating a virtual address of the memory transaction to a physical address based on the address remapping table and routing the memory transaction from the main memory to the accelerated graphics processor via the point-to-point connection based on the physical address,

wherein the second memory controller handles requests that are not meant for the accelerated graphics processor, and wherein the first memory controller is configured to reroute requests that are not meant for the accelerated graphics processor to the second memory controller via the bus.

2. The method of claim 1, wherein the address remapping table has at least one page table entry (PTE) which provides information for a translation of the virtual address to the physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address.

3. The method of claim 2, further comprising allocating a virtual page number field to the first portion.

4. The method of claim 2, further comprising allocating an offset field to the second portion.

5. The method of claim 2, further comprising providing a translation buffer comprising a plurality of entries, each entry indicating a virtual page and a corresponding physical page.

6. The method of claim 1, further comprising manufacturing the first and second memory controllers and the main memory on a single semiconductor chip.

7. The method of claim 1 wherein the first memory controller receives data in a range register defining the amount of memory that is preferentially used over other addresses for storage of data for accelerated graphics processor transactions via the point-to-point connection.

8. A multiple memory controller computer comprising:

a first memory controller and a second memory controller for controlling a main memory, wherein the first memory controller comprises a configuration register that defines a range of addresses for accelerated graphic transactions, the first memory controller being connected to the second memory controller and a central processing unit via a bus, wherein the bus is separate from a chipset of each of the memory controllers, and each memory controller is independent of the central processing unit;

a graphic address remapping table of entries, wherein the graphic address remapping table is located in the range of addresses for accelerated graphic transactions; and

an accelerated graphics processor connected to the first memory controller via a point-to-point connection that bypasses the bus;

wherein the second memory controller handles requests that are not meant for the accelerated graphics processor, the requests not meant for the accelerated graphics processor being routed from the first memory controller to the second memory controller via the bus; and

wherein the first memory controller is configured to translate a virtual address of a memory transaction associated with graphics data to a physical address based on the address remapping table and to route the memory transaction from the main memory to the accelerated graphics processor via the point-to-point connection based on the physical address.

9. The computer of claim 8, further comprising a local buffer connected to the accelerated graphics processor and wherein the local buffer and the first memory controller are logically equivalent to the accelerated graphics processor.

10. The computer of claim 8 wherein the first memory controller is configured to receive data during boot up of a computer system.

11. The computer of claim 8 wherein the first memory controller receives data in a base address register defining the starting point of memory preferentially used over other addresses for storage of accelerated graphics data for accelerated graphics processor transactions.

12. The computer of claim 11, wherein the memory preferentially used comprises graphics memory.

13. The computer of claim 8 wherein the first memory controller receives data setting a boundary address register defining the lowest address of an address remapping table.

14. The computer of claim 8 wherein the first memory controller receives data in a range register defining the amount of memory that is preferentially used over other addresses for storage of data for accelerated graphics processor transactions via the point-to-point connection.

15. The computer of claim 8 wherein the first memory controller receives data from an initialization BIOS.

16. The computer of claim 8 wherein the first memory controller receives data from the operating system API.

17. The computer of claim 8 wherein the first and second memory controllers and the main memory are manufactured on a single semiconductor chip.