Systems and methods for improving throughput of a graphics processing unit

• US 8,564,604 B2
• Filed: 04/21/2010
• Issued: 10/22/2013
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Jiao, Yang (Jeff)
• Primary Examiner(s): Wu, Xiao M.
• Assistant Examiner(s): BUTTRAM, ALAN T
• Application Number:
  US12/764,256
• Publication Number:
  US 20100201703A1
• Time in Patent Office: 1,280 Days
• Field of Search: 345/557, 345/558, 345/501, 345/522, 345/589, 712205-207
• US Class Current: 345/557
• CPC Class Codes: G11B 7/0053 Reproducing non-user data, e.g. wobbled address, prepits, BCA
• CPC Class Codes: G11B 7/0065 Recording, reproducing or erasing by using optical interference patterns, e.g. holograms

Abstract

Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to access a constant cache, a vertex attribute cache, at least one common register file, and an execution unit data path substantially simultaneously.

Claims

1. A graphics processing unit, comprising:

an execution unit configured to execute programmable shader operations, wherein the execution unit is further configured to simultaneously process operations for a plurality of threads;

a first memory forming a register file configured to accomodate register operations for all threads executed by the execution unit, the first memory being organized in a plurality of banks, with a first plurality of banks being allocated to a first plurality of the threads and a second plurality of banks being allocated to the remaining threads;

a second memory forming a constant cache configured to accomodate the fetching of constants for a plurality of shader operations executed within the execution unit, the constant cache configured to store a plurality of contexts of values for each of a plurality of types of shaders, the constant cache further configured to store a plurality of constant values and a plurality of versions of constant values in each context stored within the constant cache; and

a third memory forming a vertex attribute cache configured to accommodate the storing of vertex attributes processed by programmable shader operations executed by the execution unit.

2. The graphics processing unit of claim 1, further comprising:

a register arbiter configured to arbitrate requests to access the register file from instructions executed within the execution unit.

3. The graphics processing unit of claim 1, further comprising:

a constant cache arbiter configured to arbitrate requests to access the constant cache from instructions executed within the execution unit.

4. The graphics processing unit of claim 1, further comprising:

a vertex attribute cache arbiter configured to arbitrate requests to access the vertex attribute cache from instructions executed within the execution unit.

5. The graphics processing unit of claim 1, wherein:

the constant cache is configured to maintain two or more contexts of constants for each of geometry shader, vertex shader, and pixel shader corresponding to a header table.

6. The graphics processing unit of claim 5, wherein:

the constant cache is configured to maintain two or more versions of constants for each context corresponding to a mapping table.

7. The graphics processing unit of claim 3, further comprising:

a constant cache FIFO configured to store requested constants retrieved from the constant cache and make the requested constants available for execution of operations by the plurality of threads executing in the execution unit.

8. The graphics processing unit of claim 4, further comprising:

a vertex attribute cache FIFO configured to store requested vertex attributes retrieved from the vertex attribute cache and make the requested vertex attributes available for execution of operations by the plurality of threads executing in the execution unit.

9. A graphics processing unit comprising:

an execution unit capable of multi-threaded operation, the execution unit having a thread controller, the thread controller including a first instruction fetch arbiter and a second instruction fetch arbiter; and

a constant cache configured to accommodate the fetching of constants for a plurality of shader operations executed within the execution unit, the constant cache configured to store a plurality of contexts of values for each or a plurality of types of shaders, the constant cache further configured to store a plurality of constant values and a plurality of versions of constant values in each context stored within the constant cache;

wherein the first instruction fetch arbiter is configured to fetch instructions on behalf of at least half of a plurality of threads within the execution unit; and

wherein the second instruction fetch arbiter is configured to fetch instructions on behalf of the remainder of the plurality of threads.

10. The graphics processing unit of claim 9, wherein:

the execution unit is capable of processing at least eight active threads, wherein at least four of the at least eight active threads assigned to the first instruction fetch arbiter and the remainder of the at least eight active threads assigned to the second instruction fetch arbiter.

11. The graphics processing unit of claim 10, further comprising:

an instruction cache configured to deliver instructions to the at least eight active threads;

wherein

the first instruction fetch arbiter is configured to fetch instructions from the instruction cache system on behalf of at least half of the at least eight active threads, and the second instruction fetch arbiter is configured to fetch instructions from the instruction cache system on behalf of the remainder of the at least eight threads; and

the first instruction fetch arbiter and the second instruction fetch arbiter are configured to broadcast fetched instructions to the at least eight threads.

12. The graphics processing unit of claim 11, wherein each of the at least eight active threads further comprises:

an instruction queue configured to queue a first instruction delivered from the instruction cache, and

an instruction pre-decoder configured to determine a type of data request for a second instruction in the instruction queue.

13. The graphics processing unit of claim 12, wherein the type of data request of the second instruction is at least one chosen from:

a request to a constant cache, a request to a vertex attribute cache, a request to a common register file, and a request to the direct execution in data path unit.

14. The graphics processing unit of claim 12, wherein the instruction pre-decoder is further configured to submit the second instruction requests to at least one of:

a constant cache arbiter, a vertex attribute cache arbiter, a common register file arbiter and an execution unit data path.

15. The graphics processing unit of claim 12, wherein the execution unit is configured to fetch the first instruction and determine a type of the second instruction data requests in the instruction queue substantially simultaneously.

16. The graphics processing unit of claim 12, wherein the thread controller is configured to issue a third instruction to the execution unit data path.

17. A method of processing instructions in a graphics processing unit, comprising the steps of:

fetching a first instruction in an execution unit from an instruction cache on behalf of one of a plurality of active threads,

broadcasting the first instruction to the plurality of active threads,

queueing the first instruction in an instruction queue corresponding to at least one of the plurality of active threads,

decoding a second instruction in the instruction queue of at least one of the plurality of active threads,

submitting the second instruction as a data request to each of a constant cache, a vertex attribute cache, a first common register file, a second common register file, and an execution unit data path.

18. The method of claim 17, wherein:

the steps of fetching the first instruction and submitting the second instruction occur substantially simultaneously.

19. The method of claim 17, further comprising the step of:

submitting a request to the constant cache, wherein the constant cache maintains a header table containing a physical base address of at least one set of constants according to a shader type and context and wherein the constant cache is configured to maintain at least two contexts of constants corresponding to vertex shader, pixel shader and geometry shader.

20. The method of claim 19, wherein the constant cache further maintains a mapping table containing constants in the constant cache that have been modified and the address in the constant cache of a modified constant value.

21. The method of claim 17, wherein the constant cache, vertex attribute cache, first common register file, second common register file and execution unit data path are configured to process instructions substantially simultaneously.

22. The method of claim 17, further comprising the steps of:

issuing the second instruction to the execution unit data path when data required for execution of the instruction has been retrieved; and

outputting data from the execution unit data path via an output buffer.