Display interface buffer

• US 8,564,605 B2
• Filed: 12/27/2007
• Issued: 10/22/2013
• Est. Priority Date: 04/18/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Foreman, John B., Erickson, Jeffrey Stephen, Wright, David, Snyder, Warren
• Primary Examiner(s): Hoang, Phi
• Application Number:
  US11/965,485
• Publication Number:
  US 20080263260A1
• Time in Patent Office: 2,126 Days
• Field of Search: 345/98, 345/87, 400/490
• US Class Current: 345/564
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters

Abstract

A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

Claims

1. A device, comprising:

a general purpose memory to store data capable of being displayed on a panel;

a plurality of display drivers configured to receive data from the general purpose memory, wherein each of the display drivers is configured to drive a different portion of the panel with the data;

a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel; and

transaction descriptors reflecting a display memory map, wherein each of the transaction descriptors is configured to

direct the direct memory access controller to access the data in the general purpose memory;

associate at least one of a plurality of contiguous destination addresses, each of the contiguous destination addresses identifying at least one of the plurality of display drivers, with one of a plurality of noncontiguous source addresses each indicating a location in the general purpose memory; and

identify a data size of the data to be accessed by the direct memory access controller.

2. The device of claim 1, wherein at least one of the display drivers comprises:

a First-In-First-Out (FIFO) buffer configured to store the data received from the direct memory access controller; and

a drive voltage selector configured to select at least one of a plurality of reference voltages responsive to the data stored by the FIFO buffer, the selected reference voltage configured to drive the panel according to at least part of the data stored by the FIFO buffer.

3. The device of claim 2 where the FIFO buffer comprises:

a first memory element configured to receive data from the direct memory access controller; and

a second memory element configured to receive data from the first memory element and to provide data to the drive voltage selector.

4. The device of claim 3, wherein the first memory element and the second memory element are flip-flop buffers.

5. The device of claim 3, comprising an address decoder to decode the destination address from the direct memory access controller, wherein the destination address indicates a display driver corresponding to the display pin, wherein the second memory element receives the display data stored by the first memory element responsive to the decoded address.

6. The device of claim 2, wherein at least one of the display drivers includes a general purpose interface controller configured to receive data from the FIFO buffer and provide the data to an input-output pin as general purpose I/O data during a general purpose data mode, and wherein the input-output pin is configured to provide the data to the display drivers for presentation on the panel.

7. The device of claim 1, wherein the transaction descriptors are further configured to indicate which of the plurality of display drivers is to receive each bit of the accessed display data for presentation on the panel.

8. The device of claim 1, wherein the direct memory access controller is configured to retrieve display data from the general purpose memory responsive to at least one of the transaction descriptors, and is further configured to provide at least one of the display drivers the display data and an address that uniquely identifies the display driver to receive the display data.

9. A method comprising:

in one or more transaction descriptors, associating at least one of a plurality of contiguous destination addresses, each of the contiguous destination addresses identifying at least one of a plurality of display drivers, with one of a plurality of noncontiguous source addresses each indicating a location in a general purpose memory and identifying a data size of the data to be accessed by the direct memory access controller;

accessing the data in the general purpose memory according to the one or more transaction descriptors;

identifying one or more of the plurality of display drivers to present the accessed data on a panel by driving a column or segment of the panel; and

providing the accessed data to the identified one or more display drivers according to the transaction descriptors.

10. The method of claim 9 where at least one of the display drivers comprises:

a First-In-First-Out (FIFO) buffer configured to store the data provided according to the transaction descriptors; and

a drive voltage selector configured to select at least one a plurality of reference voltages responsive to the data stored by the FIFO buffer, wherein the selected reference voltage is configured to drive the panel according to the data stored by the FIFO buffer.

11. The method of claim 10, wherein the FIFO buffer comprises:

a first memory element configured to receive data from the direct memory access controller; and

a second memory element configured to receive the display data from the first memory element and to provide the display data to the drive voltage selector.

12. The method of claim 10, further comprising:

receiving general purpose I/O data during a general purpose data mode;

and providing the general purpose I/O data to an input-output pin via the display drivers.

13. The method of claim 12, comprising:

enabling a general purpose interface controller in the display drivers to provide general purpose I/O data to the input-output pin during the general purpose data mode; and

disabling a buffer in the display drivers from providing data to the panel via the input-output pin during the general purpose data mode.

14. The method of claim 12, comprising:

enabling a buffer in the display drivers to provide data to the panel via the input-output pin during a display driving mode; and

disabling a general purpose interface controller in the display drivers from providing general purpose I/O data to the input-output pin during the display driving mode.

15. A method comprising:

receiving one or more transaction descriptors each associating at least one of a plurality of contiguous destination addresses and identifying a data size of data to be accessed, each of the contiguous destination addresses identifying at least one of a plurality of display drivers, with one of a plurality of noncontiguous source addresses each indicating a location in a general purpose memory;

accessing the data in the general purpose memory according to the one or more received transaction descriptors;

according to the one or more received transaction descriptors, identifying at least one of the plurality of display drivers to present the accessed data on a panel by driving a column or segment of the panel; and

providing the accessed data to the at least one identified display driver according to the transaction descriptors.

16. The method of claim 15 where at least one of the display drivers comprises:

storing, in a First-In-First-Out (FIFO) buffer, the data received from the direct memory access controller; and

selecting at least one a plurality of bias voltages responsive to the data stored by the FIFO buffer, the selected bias voltage to drive the panel according to the data stored by the FIFO buffer.

17. The method of claim 16, further comprising:

receiving, in a first memory element, data from the direct memory access controller;

receiving, in a second memory element, the display data from the first memory element; and

providing the display data to the drive voltage selector.

18. The method of claim 16, further comprising:

receiving general purpose I/O data during a general purpose data mode;

and providing the general purpose I/O data to an input-output pin via the display drivers.

19. The method of claim 18, comprising:

enabling a general purpose interface controller in the display drivers to provide general purpose I/O data to the input-output pin during the general purpose data mode; and

disabling a buffer in the display drivers from providing data to the panel via the input-output pin during the general purpose data mode.

20. The method of claim 18, comprising:

enabling a buffer in the display drivers to provide data to the panel via the input-output pin during a display driving mode; and

disabling a general purpose interface controller in the display drivers from providing general purpose I/O data to the input-output pin during the display driving mode.