Multi-level cell access buffer with dual function
First Claim
Patent Images
1. A system comprising:
- a non-volatile memory;
an access buffer for writing to the non-volatile memory, the access buffer comprising;
a single-ended input for receiving a single-ended input signal having an input bit to be written to the memory;
a first latch for latching the input bit, the first latch having a double-ended input for receiving a double-ended input signal containing the input bit;
a second latch for latching a value read from a lower page of a memory location of the non-volatile memory; and
a complement signal producer for producing a complement of the single-ended input signal, the double-ended input signal comprising the complement of the single-ended input signal and the single-ended input signal.
8 Assignments
0 Petitions
Accused Products
Abstract
An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.
-
Citations
24 Claims
-
1. A system comprising:
-
a non-volatile memory; an access buffer for writing to the non-volatile memory, the access buffer comprising; a single-ended input for receiving a single-ended input signal having an input bit to be written to the memory; a first latch for latching the input bit, the first latch having a double-ended input for receiving a double-ended input signal containing the input bit; a second latch for latching a value read from a lower page of a memory location of the non-volatile memory; and a complement signal producer for producing a complement of the single-ended input signal, the double-ended input signal comprising the complement of the single-ended input signal and the single-ended input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A system comprising:
-
a non-volatile memory; and a latch circuit having a first input connected to the non-volatile memory and a second input, the latch circuit comprising a driving inverter having the second input, the system having a first mode of operation in which a first signal received at the first input from the non-volatile memory is latched by the latch circuit; the system having a second mode of operation in which a second signal received at the second input is inverted by the driving inverter. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification