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Symmetrically operating single-ended input buffer devices and methods

  • US 8,565,037 B2
  • Filed: 03/12/2013
  • Issued: 10/22/2013
  • Est. Priority Date: 12/18/2007
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.

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