Method and system for MAC and PHY synchronization for energy efficient networking

• US 8,565,269 B2
• Filed: 03/31/2009
• Issued: 10/22/2013
• Est. Priority Date: 04/15/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Diab, Wael William
• Primary Examiner(s): Chung, Hoon J
• Assistant Examiner(s): HAILE, FEBEN
• Application Number:
  US12/415,978
• Publication Number:
  US 20090257457A1
• Time in Patent Office: 1,666 Days
• Field of Search: 370/311, 370503-520, 709230-237, 713320-324
• US Class Current: 370/503
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H04J 3/0635 Clock or time synchronisation in a network timer in protocols H04L69/28
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Aspects of a method and system for MAC and PHY synchronization for energy efficient networking are provided. In this regard, an interface that enables communication between a MAC controller and a PHY device may be configured to operate in an energy saving mode. While the interface is operating in an energy saving mode, synchronization between the MAC controller and the PHY device may be maintained by one or both of adjusting a clock generated for the interface and/or communicating dummy data via the interface. The clock may be adjusted by one or more of adjusting a frequency of the clock, adjusting an amplitude of the clock, and/or duty cycling the clock. The MAC controller and/or the PHY device may generate the dummy data. The PHY device and/or the MAC controller may discard the dummy data upon receiving the dummy data.

Claims

1. A method, comprising:

transitioning a bus between a media access control device and a physical layer device from an active mode to an energy saving mode, wherein during said energy saving mode, a first part of a media access control device interface that is coupled to said bus and a first part of a physical layer device interface that is coupled to said bus are powered down; and

while in said energy saving mode, operating a second part of said media access control device interface and/or a second part of said physical layer device interface in a powered mode that enables generation of an adjusted clock signal that is transmitted across said bus, said adjusted clock signal being used to maintain synchronization between said media access control device and said physical layer device, wherein said adjusted clock signal is generated by reducing a duty cycle of a clock to a non-zero duty cycle that is lower than a duty-cycle of said clock when said bus is in said active mode, wherein said adjusted clock signal has multiple periodic cycles in a first time period having a reduced frequency and/or amplitude, and a second time period where no clock signal is generated.

2. The method according to claim 1, wherein said adjusted clock signal is generated periodically.

3. The method according to claim 1, wherein said adjusted clock signal is generated aperiodically over one or more time intervals.

4. The method according to claim 1, wherein said adjusted clock signal is reduced in frequency.

5. The method according to claim 1, wherein said adjusted clock signal is reduced in amplitude.

6. The method according to claim 1, further comprising powering up said first part of said media access control device interface and said first part of said physical layer device interface when transitioning said bus from said energy saving mode to said active mode.

7. A system for networking, the system comprising:

one or more circuits for use in a communication device, said one or more circuits comprising a media access control device, a physical layer device, and a bus between said media access control device and said physical layer device, wherein said one or more circuits are configured to;

transition said bus between said media access control device and said physical layer device from an active mode to an energy saving mode, wherein during said energy saving mode, a first part of a media access control device interface that is coupled to said bus and a first part of a physical layer device interface that is coupled to said bus are powered down; and

while in said energy saving mode, operate a second part of said media access control device interface and/or a second part of said physical layer device interface in a powered mode that enables generation of an adjusted clock signal that is transmitted across said bus, said adjusted clock signal being used to maintain synchronization between said media access control device and said physical layer device, wherein said adjusted clock signal is generated by reducing a duty cycle of a clock to a non-zero duty cycle that is lower than a duty-cycle of said clock when said bus is in said active mode wherein adjusted clock signal has multiple period cycles in a first time period having a reduced frequency and/or amplitude, and a second time period where no clock signal is generated.

8. The system according to claim 7, wherein said adjusted clock signal is generated periodically.

9. The system according to claim 7, wherein said adjusted clock signal is generated aperiodically over one or more time intervals.

10. The system according to claim 7, wherein said adjusted clock signal is reduced in frequency.

11. The system according to claim 7, wherein said adjusted clock signal is reduced in amplitude.

12. The system according to claim 7, wherein said one or more circuits are configured to power up said first part of said media access control device interface and said first part of said physical layer device interface when transitioning said bus from said energy saving mode to said active mode.

13. A method, comprising:

transitioning a bus between a media access control device and a physical layer device from an active mode to an energy saving mode, wherein during said energy saving mode, a first part of a media access control device interface that is coupled to said bus and a first part of a physical layer device interface that is coupled to said bus are powered down; and

while in said energy saving mode, operating a second part of said media access control device interface and/or a second part of said physical layer device interface in a powered mode that enables generation of an adjusted clock signal that is transmitted across said bus, said adjusted clock signal being used to maintain synchronization between said media access control device and said physical layer device, wherein said adjusted clock signal has multiple periodic cycles in a first time period hang a reduced frequency and/or amplitude, and a second time period where no clock signal is generated.

14. The method according to claim 13, wherein said adjusted clock signal is reduced in frequency.

15. The method according to claim 13, wherein said adjusted clock signal is reduced in amplitude.