Split current current digital-to-analog converter (IDAC) for dynamic device switching (DDS) of an RF PA stage

• US 8,565,694 B2
• Filed: 11/04/2011
• Issued: 10/22/2013
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Jones, David E., Levesque, Chris, Southcombe, William David, Yoder, Scott, Stockert, Terry J.
• Primary Examiner(s): Nguyen, Simon
• Application Number:
  US13/289,379
• Publication Number:
  US 20120056679A1
• Time in Patent Office: 718 Days
• Field of Search: 455/91, 4551271-1275
• US Class Current: 455/91
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control

Abstract

A split current current digital-to-analog converter (IDAC) and a radio frequency (RF) power amplifier (PA) stage are disclosed. The split current IDAC operates in a selected one of a group of DDS operating modes and provides a group of array bias signals based on the selected one of the group of DDS operating modes. Each of the group of array bias signals is a current signal. The RF PA stage includes a group of arrays of amplifying transistor elements. The RF PA stage biases at least one of the group of arrays of amplifying transistor elements based on the group of array bias signals. Further, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using at least one of the group of arrays of amplifying transistor elements that is biased.

Claims

1. Circuitry comprising:

a split current current digital-to-analog converter (IDAC) adapted to;

operate in a selected one of a plurality of dynamic device switching (DDS) operating modes; and

provide a plurality of array bias signals based on the selected one of the plurality of DDS operating modes; and

a radio frequency (RF) power amplifier (PA) stage comprising a plurality of arrays of amplifying transistor elements and adapted to bias at least one of the plurality of arrays based on the plurality of array bias signals,

wherein each of the plurality of array bias signals is a current signal.

2. The circuitry of claim 1 wherein the RF PA stage is further adapted to receive and amplify an RF stage input signal to provide an RF stage output signal using at least one of the plurality of arrays that is biased.

3. The circuitry of claim 1 further comprising control circuitry adapted to select the one of the plurality of DDS operating modes.

4. The circuitry of claim 1 wherein the plurality of array bias signals comprises a first array bias signal and a second array bias signal.

5. The circuitry of claim 4 wherein the split current IDAC is a driver stage IDAC, such that the first array bias signal is a first array driver bias signal and the second array bias signal is a second array driver bias signal.

6. The circuitry of claim 5 wherein a first array first driver bias signal and a first array second driver bias signal are based on the first array driver bias signal, and a second array first driver bias signal and a second array second driver bias signal are based on the second array driver bias signal.

7. The circuitry of claim 4 wherein the split current IDAC is a final stage IDAC, such that the first array bias signal is a first array final bias signal and the second array bias signal is a second array final bias signal.

8. The circuitry of claim 7 wherein a first array first final bias signal and a first array second final bias signal are based on the first array final bias signal, and a second array first final bias signal and a second array second final bias signal are based on the second array final bias signal.

9. The circuitry of claim 1 wherein the RF PA stage is a quadrature-phase RF PA stage.

10. The circuitry of claim 1 wherein the RF PA stage is an in-phase RF PA stage, such that the plurality of arrays of amplifying transistor elements is a first plurality of arrays of amplifying transistor elements.

11. The circuitry of claim 10 wherein the first plurality of arrays of amplifying transistor elements comprises a first array of amplifying transistor elements and a second array of amplifying transistor elements.

12. The circuitry of claim 10 further comprising a quadrature-phase RF PA stage comprising a second plurality of arrays of amplifying transistor elements.

13. The circuitry of claim 12 wherein:

the first plurality of arrays of amplifying transistor elements comprises a first array of amplifying transistor elements and a second array of amplifying transistor elements; and

the second plurality of arrays of amplifying transistor elements comprises a third array of amplifying transistor elements and a fourth array of amplifying transistor elements.

14. The circuitry of claim 1 further comprising:

a first RF PA comprising the RF PA stage and further comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

15. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature RF PA comprising the RF PA stage and coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

16. The circuitry of claim 1 further comprising:

a first RF PA comprising a first final stage, which is the RF PA stage, having a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

17. The circuitry of claim 1 further comprising:

a first RF PA having a first final stage, which is the RF PA stage, and adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

18. The circuitry of claim 1 further comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry comprising the RF PA stage.

19. The circuitry of claim 1 further comprising:

multi-mode multi-band RF power amplification circuitry comprising the RF PA stage and having at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with at least a first look-up table (LUT);

power amplifier (PA) control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least the first LUT, which is associated with at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

20. Circuitry comprising:

providing a split current current digital-to-analog converter (IDAC);

providing a radio frequency (RF) power amplifier (PA) stage comprising a plurality of arrays of amplifying transistor elements;

operating in a selected one of a plurality of dynamic device switching (DDS) operating modes;

providing a plurality of array bias signals based on the selected one of the plurality of DDS operating modes; and

biasing at least one of the plurality of arrays based on the plurality of array bias signals,

wherein each of the plurality of array bias signals is a current signal.