Software-defined radio using multi-core processor
First Claim
Patent Images
1. A radio control board comprising:
- a radio frequency (RF) controller for communicating with an RF front end coupled to the radio control board;
a bus controller for coupling the radio control board for communication with a system bus of a computing device; and
a direct memory access DMA controller for receiving digital samples of the received radio waveforms from the RF front end via the RF controller and for storing the received digital samples in a memory on the computing device via the system bus, wherein;
the bus controller passes the received digital samples from the DMA controller to the system bus for storage in the memory on the computing device;
the bus controller is configured to receive generated digital samples from the computing device via the system bus for delivery to the RF controller;
the RF controller is configured to receive the generated digital samples from the bus controller and pass the generated digital samples to the RF front end for transmission as radio waveforms;
the memory on the computing device is organized into a plurality of slots;
each slot begins with a descriptor that contains an indicator that indicates whether data in the slot has been processed;
the radio control board sets the indicator when a slot of data is written; and
a processor on the computing device determines from the indicator whether to process the data in the slot or flush the data corresponding to the slot.
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Abstract
A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing of the digital samples is carried out by one or more cores of a multi-core processor to implement a software-defined radio.
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Citations
19 Claims
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1. A radio control board comprising:
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a radio frequency (RF) controller for communicating with an RF front end coupled to the radio control board; a bus controller for coupling the radio control board for communication with a system bus of a computing device; and a direct memory access DMA controller for receiving digital samples of the received radio waveforms from the RF front end via the RF controller and for storing the received digital samples in a memory on the computing device via the system bus, wherein; the bus controller passes the received digital samples from the DMA controller to the system bus for storage in the memory on the computing device; the bus controller is configured to receive generated digital samples from the computing device via the system bus for delivery to the RF controller; the RF controller is configured to receive the generated digital samples from the bus controller and pass the generated digital samples to the RF front end for transmission as radio waveforms; the memory on the computing device is organized into a plurality of slots; each slot begins with a descriptor that contains an indicator that indicates whether data in the slot has been processed; the radio control board sets the indicator when a slot of data is written; and a processor on the computing device determines from the indicator whether to process the data in the slot or flush the data corresponding to the slot. - View Dependent Claims (2, 3, 4, 5)
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6. A method implemented on a computing device, the method comprising:
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receiving a plurality of digital samples in a memory of the computing device from a radio frequency (RF) receiver coupled to a system bus of the computing device, the memory of the computing device being organized into a plurality of slots, each slot of the plurality of slots beginning with a descriptor that contains an indicator; for a slot of the plurality of slots, setting the indicator for the slot in response to determining that a digital sample of the plurality of digital samples is written to the slot; using a first core of a multi-core processor to perform at least a portion of physical layer processing of the digital sample as a first kernel thread running on the first core; using a second core of the multi-core processor to perform media access control (MAC) layer processing of the digital sample as a second kernel thread running on the second core; and determining, based at least in part on the indicator, whether the digital sample in the slot has been processed. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. One or more computer-readable storage media maintaining processor-executable instructions that, when executed by a processor, implement modules comprising:
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a management module for controlling a radio control board for delivery of digital samples between a radio frequency (RF) transceiver and a memory on a computing device via a system bus; a media access control module for performing MAC layer processing of the digital samples on one or more first cores of a multi-core processor; and a physical layer module for performing physical layer processing of the digital samples, at least in part, on one or more second cores of the multi-core processor, wherein; the memory on the computing device is organized into a plurality of slots; a slot of the plurality of slots is associated with an indicator that indicates whether a digital sample of the plurality of digital samples in the slot has been processed; and the indicator is set when the digital sample in the slot is written. - View Dependent Claims (17, 18, 19)
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Specification