Software-defined radio using multi-core processor

• US 8,565,811 B2
• Filed: 08/04/2009
• Issued: 10/22/2013
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Tan, Kun, Zhang, Jiansong, Zhang, Yongguang
• Primary Examiner(s): Nguyen, Duc M
• Application Number:
  US12/535,415
• Publication Number:
  US 20110035522A1
• Time in Patent Office: 1,540 Days
• Field of Search: 455/550.1, 455/552.1, 455/553.1, 455/556.1, 455/557, 455/90.1, 455/90.2, 711/100, 712/220
• US Class Current: 455/550.1
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing of the digital samples is carried out by one or more cores of a multi-core processor to implement a software-defined radio.

Claims

1. A radio control board comprising:

a radio frequency (RF) controller for communicating with an RF front end coupled to the radio control board;

a bus controller for coupling the radio control board for communication with a system bus of a computing device; and

a direct memory access DMA controller for receiving digital samples of the received radio waveforms from the RF front end via the RF controller and for storing the received digital samples in a memory on the computing device via the system bus, wherein;

the bus controller passes the received digital samples from the DMA controller to the system bus for storage in the memory on the computing device;

the bus controller is configured to receive generated digital samples from the computing device via the system bus for delivery to the RF controller;

the RF controller is configured to receive the generated digital samples from the bus controller and pass the generated digital samples to the RF front end for transmission as radio waveforms;

the memory on the computing device is organized into a plurality of slots;

each slot begins with a descriptor that contains an indicator that indicates whether data in the slot has been processed;

the radio control board sets the indicator when a slot of data is written; and

a processor on the computing device determines from the indicator whether to process the data in the slot or flush the data corresponding to the slot.

2. The radio control board according to claim 1, wherein the bus is a Peripheral Component Interconnect Express (PCIe) bus.

3. The radio control board according to claim 1, further comprising an onboard memory on the radio control board for at least one of:

storing the generated digital samples temporarily prior to passing the generated digital samples to the RF front end;

or

storing the received digital samples temporarily prior to passing the received digital samples to the memory on the computing device.

4. The radio control board according to claim 1, further comprising an onboard memory on the radio control board for storing a pre-generated ACK waveform, wherein:

during demodulation of a received frame, the pre-generated ACK is prepared for sending in response to the frame for providing an acknowledgement of receiving the received frame, and

following a check of the received frame, the pre-generated ACK is delivered to the RF front end for transmission to acknowledge receipt of the received frame.

5. The radio control board according to claim 1, further comprising:

a first FIFO buffer on the radio control board located between the RF front end and the DMA controller for temporarily storing the digital samples received from the RF front end prior to the DMA controller storing the digital samples on the memory of the computing device; and

a second FIFO buffer on the radio control board between the bus controller and the RF front end for temporarily storing processed digital samples received from the computing device prior to delivery of the generated digital samples to the RF front end.

6. A method implemented on a computing device, the method comprising:

receiving a plurality of digital samples in a memory of the computing device from a radio frequency (RF) receiver coupled to a system bus of the computing device, the memory of the computing device being organized into a plurality of slots, each slot of the plurality of slots beginning with a descriptor that contains an indicator;

for a slot of the plurality of slots, setting the indicator for the slot in response to determining that a digital sample of the plurality of digital samples is written to the slot;

using a first core of a multi-core processor to perform at least a portion of physical layer processing of the digital sample as a first kernel thread running on the first core;

using a second core of the multi-core processor to perform media access control (MAC) layer processing of the digital sample as a second kernel thread running on the second core; and

determining, based at least in part on the indicator, whether the digital sample in the slot has been processed.

7. The method according to claim 6, wherein the one or more first cores are dedicated to processing the digital sample while one or more second cores of the multi-core processor execute one or more applications.

8. The method according to claim 7, wherein the one or more first cores are dedicated to processing of the digital sample by initiating a kernel thread for processing the digital sample, and raising the priority of the thread and/or an interrupt request level of the kernel thread so that the kernel thread runs exclusively on a particular first core until termination.

9. The method according to claim 8, further comprising removing interrupt handlers for installed devices from the particular first core to prevent the particular first core from being interrupted by hardware until termination of the kernel thread.

10. The method according to claim 6, further comprising:

passing the plurality of digital samples from the RF receiver to the memory of the computing device by a radio control board coupled between the RF receiver and the memory of the computing device,

wherein the plurality of digital samples are passed from the RF receiver to the memory of the computing device on a Peripheral Component Interconnect Express (PCIe) bus.

11. The method according to claim 6, further comprising using single instruction multiple data (SIMD) instructions to simultaneously process an array of the plurality of digital samples during at least one of the physical layer processing or the media access control (MAC) layer processing of the plurality of digital samples.

12. The method according to claim 6, further comprising:

pre-calculating one or more lookup tables for one or more physical layer algorithms and/or one or media access control (MAC) layer algorithms;

storing the one or more lookup tables in a cache associated with the one or more first cores; and

accessing the lookup tables during processing of the digital sample in place of performing calculations for the corresponding algorithms during the physical layer processing and/or the MAC layer processing of the digital sample.

13. The method according to claim 6, further comprising performing physical layer processing of the digital sample using at least two first cores of the multi-core processor, wherein a first sub-pipeline of functional physical layer blocks is executed on a first one of the first cores and a second sub-pipeline of physical layer blocks is executed on a second one of the first cores.

14. The method according to claim 13, wherein one of the first cores acts as a consumer of data and the other first core acts as a producer of data, further comprising:

providing a circular First In First Out (FIFO) buffer between the consumer and the producer, wherein the FIFO buffer includes a plurality of data slots, wherein each data slot includes an indicator as to whether the data slot is full or empty, wherein the FIFO buffer further includes a pointer for the consumer and a pointer for the producer;

wherein the consumer pointer follows the producer pointer to take data from the FIFO for consumption by the consumer.

15. The method according to claim 6, the method further comprising:

raising the priority and/or an interrupt request level of each of the first kernel thread and the second kernel thread so that each kernel thread runs exclusively on the corresponding first core and second core until termination of the respective kernel thread.

16. One or more computer-readable storage media maintaining processor-executable instructions that, when executed by a processor, implement modules comprising:

a management module for controlling a radio control board for delivery of digital samples between a radio frequency (RF) transceiver and a memory on a computing device via a system bus;

a media access control module for performing MAC layer processing of the digital samples on one or more first cores of a multi-core processor; and

a physical layer module for performing physical layer processing of the digital samples, at least in part, on one or more second cores of the multi-core processor, wherein;

the memory on the computing device is organized into a plurality of slots;

a slot of the plurality of slots is associated with an indicator that indicates whether a digital sample of the plurality of digital samples in the slot has been processed; and

the indicator is set when the digital sample in the slot is written.

17. The one or more computer-readable storage media according to claim 16, wherein:

the management module further includes a direct memory access (DMA) manager for controlling a DMA controller on the radio control board,

the DMA controller delivers the digital samples from the RF transceiver to a DMA memory portion of the memory on the computing device,

the DMA manager sets a flag on the digital samples when written to the memory, and

the processor processing the digital samples checks the flag before reading data in a cache to avoid inconsistency between the data in the cache and the data in the DMA memory.

18. The one or more computer-readable storage media according to claim 16, wherein the management module includes a Peripheral Component Interconnect Express (PCIe) driver for controlling the radio control board for delivery of the digital samples between the radio frequency (RF) transceiver and the memory on the computing device via the system bus, wherein the system bus is a PCIe bus.

19. The one or more computer-readable storage media according to claim 16, wherein the media access control module and the physical layer module are controlled by the management module for processing digital samples on the multi-core processor.