Method and system for switching between subnetwork operation and full network operation

• US 8,566,466 B2
• Filed: 06/05/2003
• Issued: 10/22/2013
• Est. Priority Date: 06/10/2002
• Status: Active Grant

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Muth, Matthias
• Primary Examiner(s): Armouche, Hadi
• Assistant Examiner(s): Harris, Christopher C
• Application Number:
  US10/517,246
• Publication Number:
  US 20050204204A1
• Time in Patent Office: 3,792 Days
• Field of Search: 709/230, 709/224, 370/241, 370/432, 713/320, 713/323
• US Class Current: 709/230
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus

Abstract

In order further to develop a method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), together with a corresponding system (100) in such a way that the nodes (22, 28) and/or the users (32, 38) in the network, i.e. on the databus (10), may be simply yet effectively woken, it is proposed that the system (100) be changed over from subnetwork operation (T) to full network operation (G) through the detection of at least one defined, especially continuous and/or especially symmetrical signal level pattern (62, 64) in the data traffic on the system (100).

Claims

1. A method for changing over a serial databus system, the method comprising:

operating the system in subnetwork operation in which at least one node and/or at least one chip unit of the system is in a state of reduced current consumption and is not addressed and/or not activated by a signal level of data traffic on the system;

detecting at least one defined continuous and/or symmetrical signal level pattern in the data traffic on the system; and

in response to detection of the at least one defined continuous and/or symmetrical signal level pattern in the data traffic, changing the system from the subnetwork operation to a full network operation in which all the nodes and/or all the chip units of the system are addressed and/or activated by the signal level of the data traffic on the system.

2. A method as claimed in claim 1, characterized in that the signal level pattern does not otherwise occur in the data traffic.

3. A method as claimed in claim 1, characterized in that the signal level pattern is detected by at least one node in the reduced current consumption state and/or by at least one chip unit in the reduced current consumption state.

4. A method as claimed in claim 1 performed at least partly by a transceiver unit, characterized in that the transceiver unit is connected to at least one Controller Area Network (CAN) bus, and is in communication with at least one microcontroller unit which is provided to carry out at least one application.

5. A method as claimed in claim 4 performed at least partly by the transceiver unit characterized by at least one control logic associated with the transceiver unit and/or implemented in the transceiver unit.

6. A method as claimed in claim 4 performed at least partly by a voltage regulator which is connected to at least one battery unit, and which is in communication with the at least one transceiver unit which voltage regulator is configured to supply a voltage to at least one microcontroller unit, provided to execute at least one application, in the event of detection, by the transceiver unit, of at least one defined, in particular continuous and/or in particular symmetrical signal level pattern in at least one incoming message associated with at least one application and occurring on at least one Controller Area Network (CAN) bus.

7. A method as claimed in claim 4 performed at least partly by a chip unit, in particular a system chip unit, for addressing and/or activating at least one microcontroller unit which is provided to carry out at least one application and which is associated with at least one Controller Area Network (CAN) bus;

characterized by the at least one transceiver unit and at least one voltage regulator, which is connected to at least one battery unit, and which is in communication with at the at least one transceiver unit, the voltage regular being configured to supply a voltage to the at least one microcontroller unit.

8. A method as claimed in claim 4 performed at least partly by a microcontroller unit provided to carry out at least one application and associated with at least one Controller Area Network (CAN) bus, which microcontroller unit is to be supplied with a voltage only if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected in at least one incoming message associated with at least one application and occurring on the databus, by the at least one transceiver unit.

9. A method as claimed in claim 8 performed at least partly by the microcontroller unit characterized in that the microcontroller unit is activated by the transceiver unit.

10. A serially networked system comprising:

a serial databus; and

a plurality of chip units that are connected to the serial databus via respective nodes, the chip units being configured to;

operate the system in subnetwork operation in which at least one node and/or at least one chip unit of the system is in a state of reduced current consumption and is not addressed and/or not activated by a signal level of data traffic on the system;

detect at least one defined continuous and/or symmetrical signal level pattern in the data traffic on the system; and

in response to detection of the at least one defined continuous and/or symmetrical signal level pattern in the data traffic, change the system from the subnetwork operation to a full network operation in which all the nodes and/or all the chip units of the system are addressed and/or activated by the signal level of the data traffic on the system.

11. A system as claimed in claim 10, characterized in that the signal level pattern does not otherwise occur in the data traffic.

12. A system as claimed in claim 10, characterized in that the signal level pattern is detected by at least one node and/or chip unit in the reduced current consumption state.

13. A system as claimed in claim 10, characterized in that the system comprises at least one Controller Area Network (CAN) bus.

14. A system as claimed in claim 10, characterized in that the chip unit takes the form of at least one chip unit, in particular at least one system chip unit, and/or at least one microcontroller unit provided for carrying out at least one application.