Flash management using sequential techniques

• US 8,566,505 B2
• Filed: 04/15/2008
• Issued: 10/22/2013
• Est. Priority Date: 04/15/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Smart Storage Systems Incorporated (Western Digital Corporation)
• Inventors: Kilzer, Kevin L., Ellis, Robert W., Sterbenz, Rudolph J.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US12/103,273
• Publication Number:
  US 20090259800A1
• Time in Patent Office: 2,016 Days
• Field of Search: 711/103, 711/100, 711/154
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.

Claims

1. A method for flash memory management, comprising:

receiving payload data from a host;

writing the payload data in the order it was received to an erase block in a flash memory device; and

providing a logical to physical (L2P) table and a physical erase block (PEB) table configured to locate the payload data written to the flash memory device, wherein the L2P table and the PEB table are contained entirely in a random access memory;

wherein writing the payload data includes;

locating a target page in the erase block,

combining the payload data with metadata,

writing the payload data and the metadata to the target page in the erase block,

updating the L2P table,

updating the PEB table, and

responsive to page offset information indicating all pages in the erase block except an index page are full, writing index information for the erase block to the index page in the erase block.

2. The method of claim 1, wherein writing the payload data in the order it was received includes writing the payload data in a sequential manner within the erase block.

3. The method of claim 1, wherein the erase block includes an index page that stores erase block index information for the payload data written to the erase block.

4. The method of claim 3, further comprising using the index page to construct at least one of the L2P table and the PEB table when the flash memory device is powered on.

5. The method of claim 3, wherein the index page is the last physical page in the erase block.

6. The method of claim 1, wherein the PEB table includes information that maps consecutive pages of the payload data to different flash chips.

7. The method of claim 1, wherein the PEB table includes a bitfield indicating if a page is obsolete.

8. The method of claim 1, wherein the PEB table is configured to prevent at least one erase block from being used.

9. The method of claim 1, wherein the writing the payload data in the order it was received includes:

writing a first page of the payload data received from the host to a first erase block in the flash memory device;

writing a second page of the payload data received from the host to a second erase block in the flash memory device; and

writing a third page of the payload data received from the host to the first erase block in the flash memory device;

wherein the first page of the payload data, the second page of the payload data, and the third page of the payload data are received in sequential order from the host, and wherein the third page of the payload data is written to the first erase block in a location following the first page of the payload data.

10. A method for data management on a flash memory device, comprising:

providing payload data to a flash memory device;

writing the payload data to an erase block on the flash memory device in the order it was received; and

mapping a location of the payload data on the flash memory device, wherein the mapping includes providing a logical to physical (L2P) table and a physical erase block (PEB) table contained entirely in a random access memory, and wherein the L2P table and the PEB table are configured to locate the payload data written to the flash memory device;

wherein writing the payload data includes;

locating a target page in the erase block,

combining the payload data with metadata,

writing the payload data and the metadata to the target page in the erase block,

updating the L2P table,

updating the PEB table, and

responsive to page offset information indicating all pages in the erase block except an index page are full, writing index information for the erase block to the index page in the erase block.

11. The method of claim 10, wherein the erase block containing the payload data includes an index page that stores erase block index information for the payload data written to pages in the erase block.

12. The method of claim 10, wherein the erase block containing the payload data includes an index page that stores erase block index information for the payload data written to pages in a different erase block.

13. The method of claim 10, wherein all data structures needed to locate the payload data written to the flash memory device are located in their entirety in the random access memory.

14. A solid state drive, comprising:

a flash controller configured to communicate with a host;

a random access memory containing a logical to physical (L2P) table and a physical erase block (PEB) table, wherein the L2P table and the PEB table are configured to locate payload data written to the solid state drive, and wherein the L2P table and the PEB table are contained entirely in the random access memory; and

at least one flash chip configured to receive the payload data from the flash controller,

wherein the flash controller is configured to write the payload data to the at least one flash chip in a manner which preserves time order of the payload data including;

locating a target page in the erase block,

combining the payload data with metadata,

writing the payload data and the metadata erase block,

updating the L2P table,

updating the PEB table, and

responsive to page offset information indicating all pages in the erase block except an index page are full, writing index information for the erase block to the index page in the erase block.

15. The solid state drive of claim 14, wherein the flash controller includes a buffer-host machine, a media-buffer machine, a data buffer, a local buffer, and a sequence and control machine.

16. The solid state drive of claim 14, wherein the flash controller is configured to write the payload data in a sequential manner within an erase block.

17. A data storage system, comprising:

a memory configured for block-based erase operations;

a controller coupled to the memory, wherein the controller is configured to write incoming payload data to the memory in the order the payload data is received; and

a random access memory containing a logical to physical (L2P) table and a physical erase block (PEB) table, wherein the L2P table and the PEB table are configured to locate the payload data written to the data storage system, and wherein the L2P table and the PEB table are contained entirely in the random access memory;

wherein the controller is for;

locating a target page in the erase block,

combining the payload data with metadata,

writing the payload data and the metadata to the target page in the erase block,

updating the L2P table,

updating the PEB table, and

responsive to page offset information indicating all pages in the erase block except an index page are full, writing index information for the erase block to the index page in the erase block.

18. The data storage system of claim 17, wherein the controller includes a buffer-host machine, a media-buffer machine, a data buffer, a local buffer, and a sequence and control machine.

19. The data storage system of claim 17, wherein the controller is configured to write the incoming payload data in a sequential manner within an erase block.

20. The data storage system of claim 17, wherein the PEB table tracks pages within erase blocks of the memory such that when a particular page is deemed unusable for storing the payload data, other pages within the same erase block of the memory may still be used for storing the payload data.