Data storage device capable of recognizing and controlling multiple types of memory chips

• US 8,566,507 B2
• Filed: 08/07/2009
• Issued: 10/22/2013
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Sprinkle, Robert S., Swing, Andrew T., Borchers, Albert T.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US12/537,704
• Publication Number:
  US 20100262757A1
• Time in Patent Office: 1,537 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips.

Claims

1. A data storage device comprising:

a first memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the first memory board and the controller board are disposed on physically separate printed circuit boards that are connected together using a ball grid array connector and wherein the controller board comprises;

a PCI-e interface to a host,

a field programmable gate array (FPGA) controller that is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize a type of the memory chips on the first memory board by reading the device characteristics of the memory chips stored in the memory module on the first memory board, including memory chips manufactured by different vendors, single-level cell (SLC) NAND flash memory chips and multi-level cell (MLC) NAND flash memory chips such that the data storage device is configurable with different types of memory chips based on one or more applications operating on the host,

use the device characteristics of the memory chips to configure the controller based on the types of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips by translating the commands to native memory chip commands based on the type of the memory chips on the first memory board; and

a memory module disposed on the controller board that is operably coupled to the FPGA controller and that is configured to store one or more images for the FPGA controller including firmware for use by the FPGA controller to automatically recognize the type of the memory chips.

2. The data storage device of claim 1 wherein the FPGA controller is arranged and configured to automatically recognize the type of the memory chips on the first memory board upon power up of the first memory board and the FPGA controller board.

3. The data storage device of claim 1 further comprising a second memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the FPGA controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the second memory board by reading the device characteristics of the memory chips stored in the memory module on the second memory board,

use the device characteristics of the memory chips to configure the controller based on the types of memory chips on the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board by translating the commands to native memory chip commands based on the type of the memory chips on the first memory board and the second memory board.

4. The data storage device of claim 3 further comprising a third memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips and a fourth memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips wherein:

the controller board is arranged and configured to disconnect from the first memory board and the second memory board and to operably connect to the third memory board and the fourth memory board, and

the FPGA controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the third memory board and on the fourth memory board by reading the device characteristics of the memory chips stored in the memory module on the third memory board and stored in the memory module on the fourth memory board, wherein the type of the memory chips on the third memory board and the fourth memory board are a same type and the type of the memory chips on the third memory board and the fourth memory board are a different type from the memory chips on the first memory board and the second memory board,

use the device characteristics of the memory chips to configure the controller based on the types of the memory chips on the third memory board and the fourth memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the third memory board and the fourth memory board by translating the commands to native memory chip commands based on the type of the memory chips on the third memory board and the fourth memory board.

5. The data storage device of claim 1 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

6. The data storage device of claim 1 wherein the memory chips comprise phase change memory (PCM) chips.

7. The data storage device of claim 1 wherein the memory chips comprise flash memory chips.

8. A computing device comprising:

a host; and

a data storage device, the data storage device comprising;

a first memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips, and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the first memory board and the controller board are disposed on physically separate printed circuit boards that are connected together using a ball grid array connector and wherein the controller board comprises;

a PCI-e interface to the host, and

a field programmable gate array (FPGA) controller that is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize a type of the memory chips on the first memory board by reading the device characteristics of the memory chips stored in the memory module on the first memory board, including memory chips manufactured by different vendors, single-level cell (SLC) NAND flash memory chips and multi-level cell (MLC) NAND flash memory chips such that the data storage device is configurable with different types of memory chips based on one or more applications operating on the host,

use the device characteristics of the memory chips to configure the controller based on the types of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips by translating the commands to native memory chip commands based on the type of the memory chips on the first memory board; and

a memory module disposed on the controller board that is operably coupled to the FPGA controller and that is configured to store one or more images for the FPGA controller including firmware for use by the FPGA controller to automatically recognize the type of the memory chips.

9. The computing device of claim 8 further comprising a second memory board comprising multiple memory chips and a memory module storing device characteristics of the memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the FPGA controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the second memory board by reading the device characteristics of the memory chips stored in the memory module on the second memory board,

use the device characteristics of the memory chips to configure the controller based on the types of memory chips on the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board by translating the commands to native memory chip commands based on the type of the memory chips on the first memory board and the second memory board.

10. The computing device of claim 8 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

11. The computing device of claim 8 wherein the memory chips comprise phase change memory (PCM) chips.

12. The computing device of claim 8 wherein the memory chips comprise flash memory chips.

13. A method, comprising:

receiving power at a controller board, wherein the controller board comprises a PCI-e interface to a host and a field programmable gate array (FPGA) controller, the FPGA controller being configured to control command processing for multiple different types of memory chips;

querying a first memory board for one or more device characteristics of multiple memory chips secured to the first memory board from a memory module on the first memory board storing the device characteristics of the memory chips, wherein the first memory board and the controller board are disposed on physically separate printed circuit boards that are connected together using a ball grid array connector;

automatically recognizing a type of the memory chips on the first memory board based on the one or more device characteristics of the memory chips, including memory chips manufactured by different vendors, single-level cell (SLC) NAND flash memory chips and multi-level cell (MLC) NAND flash memory chips such that the data storage device is configurable with different types of memory chips based on one or more applications operating on the host;

using the device characteristics to configure the controller based on the types of the memory chips on the first memory board;

receiving commands from the host using the interface;

executing the commands using the memory chips by translating the commands to native memory chip commands based on the type of the memory chips on the first memory board; and

storing one or more images for the FPGA controller including firmware for use by the FPGA controller to automatically recognize the type of the memory chips.

14. The method as in claim 13 further comprising:

connecting a second memory board to the controller board, the second memory board comprising multiple memory chips and a memory module storing device characteristics on the memory chips;

automatically recognizing a type of the memory chips on the second memory board by reading the device characteristics of the memory chips stored in the memory module on the second memory board; and

using the device characteristics to configure the FPGA controller based on the types of the memory chips on the second memory board,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the first memory board and the second memory board by translating the command to native memory chip commands based on the type of the memory chips on the first memory board and the second memory board.

15. The method as in claim 14 further comprising:

disconnecting the first memory board and the second memory board from the controller board;

connecting a third memory board and a fourth memory board to the controller board, the third memory board and the fourth memory board each comprising multiple memory chips and a memory module storing device characteristics of the memory chips;

automatically recognizing a type of the memory chips on the third memory board and on the fourth memory board by reading the device characteristics of the memory chips stored in the memory module on the third memory board and on the fourth memory board, wherein the type of the memory chips on the third memory board and the fourth memory board are a same type and the type of the memory chips on the third memory board and the fourth memory board are a different type from the memory chips on the first memory board and the second memory board; and

using the device characteristics of the memory chips to configure the FPGA controller based on the types of the memory chips on the third memory board and the fourth memory board,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the third memory board and the fourth memory board by translating the command to native memory chip commands based on the type of the memory chips on the third memory board and the fourth memory board.

16. The method as in claim 13 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

17. The method as in claim 13 wherein the memory chips comprise phase change memory (PCM) chips.

18. The method as in claim 13 wherein the memory chips comprise flash memory chips.