RAID configuration in a flash memory data storage device

• US 8,566,508 B2
• Filed: 08/07/2009
• Issued: 10/22/2013
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US12/537,748
• Publication Number:
  US 20100262762A1
• Time in Patent Office: 1,537 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition.

Claims

1. A method of storing data in a flash memory data storage device that includes a plurality of memory chips, the method comprising:

determining a number of memory chips in the data storage device, wherein a first portion of the plurality of memory chips is implemented in a first memory channel and a second portion of the plurality of memory chips is implemented in a second memory channel;

defining, via a host coupled to the data storage device, a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips;

defining a second partition of the data storage device via the host coupled to the data storage device, wherein the second partition includes a second subset of the plurality of memory chips;

writing first data to the first partition while reading data from the second partition; and

writing the first data to the second partition while reading data from the first partition,

wherein;

the first subset includes one or more memory chips of the first memory channel and one or more memory chips of the second memory channel;

the first subset does not include any memory chips of the second subset;

the second subset does not include any memory chips of the first subset;

the first partition and the second partition implement different data storage areas in the data storage device; and

a boundary between the first partition and second partition is defined by the first subset of memory chips and the second subset of memory chips.

2. The method of claim 1, further comprising:

writing second data to the first partition, while reading data from the second partition;

writing the second data to the second partition while reading data from the first partition; and

for N=3rd to at least 10th;

writing N data to the first partition while reading data from the second partition; and

writing the N data to the second partition while reading data from the first partition.

3. The method of claim 1, wherein determining the number memory chips in the data storage device includes transmitting information from the data storage device to the host indicating the number of memory chips in the data storage device.

4. The method of claim 3, wherein the transmitted information includes information about a physical architecture of the data storage device, including information about connections between particular memory chips and particular channels of the data storage device.

5. The method of claim 1, further comprising defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips.

6. The method of claim 1, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method further comprising:

determining a number of the physical channels;

determining a first subset of the number of channels, wherein channels of the first subset of channels are operably connected only to memory chips of the first subset of memory chips; and

determining a second subset of the number of channels, wherein channels of the second subset of channels are operably connected only to memory chips of the second subset of memory chips.

7. The method of claim 6, further comprising:

defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

8. The method of claim 1, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, the method further comprising:

determining a number of the physical channels,

wherein the determined channels are operably connected to memory chips of the first subset of memory chips and are operably connected to memory chips of the second subset of memory chips.

9. The method of claim 8, further comprising:

defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

10. The method of claim 1, further comprising:

receiving an indication that a memory chip of the first partition has failed or is likely to fail;

re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of memory chips,

wherein the third subset is different from the first subset, and

wherein the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset.

11. The method of claim 10,

wherein re-defining the first partition includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.

12. An apparatus comprising:

a flash memory data storage device including a plurality of memory chips, wherein a first portion of the plurality of memory chips is implemented in a first memory channel and a second portion of the plurality of memory chips is implemented in a second memory channel;

a host operably coupled to the data storage device via an interface, the host comprising;

a configuration detection engine configured to detect a number of memory chips in the data storage device;

a partition engine configured to define a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips and a second partition of the data storage device, wherein the second partition includes a second subset of the plurality of memory chips;

a driver configured to;

write first data to the first partition while reading data from the second partition; and

write the first data to the second partition while reading data from the first partition,

wherein;

the first subset includes one or more memory chips of the first memory channel and one or more memory chips of the second memory channel;

the first subset does not include any memory chips of the second subset;

the second subset does not include any memory chips of the first subset;

the first partition and the second partition implement different data storage areas in the data storage device; and

a boundary between the first partition and second partition is defined by the first subset of memory chips and the second subset of memory chips.

13. The apparatus of claim 12, wherein the driver is further configured to:

write second data to the first partition;

read data from the second partition while the second data is being written to the first partition;

writing the second data to the second partition while reading data from the first partition; and

for N=3rd to at least 10th to;

write N data to the first partition;

read data from the second partition while the N data is being written to the first partition; and

write the N data to the second partition while reading data from the first partition.

14. The apparatus of claim 12, wherein the data storage device is configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of memory chips in the data storage device.

15. The apparatus of claim 14, wherein the transmitted information includes information about a physical architecture of the data storage device, including information about connections between particular memory chips and particular channels of the data storage device.

16. The apparatus of claim 12, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.

17. The apparatus of claim 12, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, and

wherein the configuration detection engine is further configured to detect a number of the physical channels;

wherein the partition engine is further configured to determine a first subset of the number of channels, wherein channels of the first subset of channels are operably connected only to memory chips of the first subset of memory chips; and

wherein the partition engine is further configured to determine a second subset of the number of channels, wherein channels of the second subset of channels are operably connected only to memory chips of the second subset of memory chips.

18. The apparatus of claim 17, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

19. The apparatus of claim 17, wherein the first partition includes memory chips that are operably connected to a single channel.

20. The apparatus of claim 12,

wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips,

wherein the plurality of physical channels are operably connected to memory chips of the first subset of memory chips and are operably connected to memory chips of the second subset of memory chips.

21. The apparatus of claim 12, wherein the partition engine is further configured to:

receive an indication that a memory chip of the first partition has failed or is likely to fail;

re-define the first partition of the data storage device to include a third subset of the plurality of memory chips,

wherein the third subset is different from the first subset, and

wherein the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset.

22. The apparatus of claim 21,

wherein re-defining the first partition to include the third subset of the plurality of memory chips includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.