Memory subsystem
First Claim
1. A memory subsystem comprising:
- a memory; and
a memory controller thatprovides one or more data-stream interfaces coupled to receive a data-stream input that includes a plurality of data organized according to a predetermined data structure,provides a random-access interface to individual memory cells and to two-dimensional memory regions within the memory, each individual memory cell and each two-dimensional memory region being associated with a (x, y) coordinate pair that describes a corresponding location within the memory,arbitrates among the data-stream interfaces and random-access interface to serialize concurrently requested memory accesses received through the data-stream interfaces and random-access interface,carries out memory accesses requested through the data-stream interfaces by writing the data-stream input to the memory, andcarries out single-memory-cell and two-dimensional-memory-cell-region memory accesses requested through the random-access interface by reading values from, or writing values to, the individual memory cells and the two-dimensional memory-cell regions in the memory.
2 Assignments
0 Petitions
Accused Products
Abstract
Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device. In alternative embodiments of the present invention, the memory controller and memory are together integrated within a computational engine or another electronic device. Alternative embodiments of the present invention include a multi-access memory that interfaces to a simpler memory controller for connection to, or integration within, a computational engine or other electronic device.
-
Citations
27 Claims
-
1. A memory subsystem comprising:
-
a memory; and a memory controller that provides one or more data-stream interfaces coupled to receive a data-stream input that includes a plurality of data organized according to a predetermined data structure, provides a random-access interface to individual memory cells and to two-dimensional memory regions within the memory, each individual memory cell and each two-dimensional memory region being associated with a (x, y) coordinate pair that describes a corresponding location within the memory, arbitrates among the data-stream interfaces and random-access interface to serialize concurrently requested memory accesses received through the data-stream interfaces and random-access interface, carries out memory accesses requested through the data-stream interfaces by writing the data-stream input to the memory, and carries out single-memory-cell and two-dimensional-memory-cell-region memory accesses requested through the random-access interface by reading values from, or writing values to, the individual memory cells and the two-dimensional memory-cell regions in the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A multi-access memory comprising:
-
a rectilinear grid of memory cells, each memory cell storing a bit of information; a row demultiplexer that directs bits from a data stream into memory cells, by using data-transfer shift operations, the bits organized in the data stream according to a predetermined data structure and being transferred to a row of memory cells selected by the row demultiplexer within the rectilinear grid of memory cells; and a row-demultiplexer-and-column-demultiplexer pair that directs a bit received in a random-memory-access WRITE request into a memory cell selected by the row-demultiplexer-and-column-demultiplexer pair and that retrieves a bit requested by a random-memory-access READ request from a memory cell selected by the row-demultiplexer-and-column-demultiplexer pair, each request of the WRITE and READ requests being associated with a (x, y) coordinate pair that describes the address of the memory cell within the rectilinear grid of memory cells. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
-
Specification