Refresh management of memory modules

• US 8,566,516 B2
• Filed: 10/30/2007
• Issued: 10/22/2013
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Schakel, Keith R., Rajan, Suresh Natarajan, Smith, Michael John Sebastian, Wang, David T.
• Primary Examiner(s): LO, KENNETH M
• Application Number:
  US11/929,631
• Publication Number:
  US 20080109597A1
• Time in Patent Office: 2,184 Days
• Field of Search: 711/106, 711/173
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.

Claims

1. A memory module comprising:

2*N dynamic random access memory (DRAM) devices each having a capacity of M, wherein the 2*N DRAM devices comprising;

a first group of N DRAM devices; and

a second group of N DRAM devices, wherein each of the N DRAM devices in the first group shares a distinct refresh control signal with a respective DRAM device in the second group;

emulation logic configured to emulate an interface protocol of two emulated DRAM devices each having a capacity of N*M, wherein a first of the two emulated DRAM devices includes the N DRAM devices from the first group, and a second of the two emulated DRAM devices includes the N DRAM devices from the second group;

an interface circuit configured to receive from a memory controller a refresh command for the two emulated DRAM devices, the interface circuit including;

a calculation unit configured to determine offset timings for N independently controlled staggered refresh cycles, wherein exactly one DRAM device from the first group and one DRAM device from the second group are refreshed in each of the independently controlled staggered refresh cycles, the offset timings providing timings of each of the independently controlled staggered refresh cycles; and

a scheduler configured to order independently controlled staggered refresh commands directed to the 2*N DRAM devices in the first and the second groups based on the offset timings determined by the calculation unit.

2. The memory module of claim 1, wherein the interface circuit further comprises:

a measurement unit configured to perform analog signal measurements and to determine a configuration of DRAM devices;

wherein the calculation unit is configured to determine the independently controlled staggered refresh cycles based on measurements received from the measurement unit and the refresh command received from the memory controller.

3. The memory module of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine analog pin characteristics of DRAM devices.

4. The memory module of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine timing responses at selected logic threshold levels.

5. The memory module of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine a timing response at a peak detected voltage change, a duration and a response ring.

6. The memory module of claim 2, wherein the measurement unit is further configured to perform a series of measurements to determine an operating temperature of each of the DRAM devices.

7. The memory module of claim 1, wherein the calculation unit is configured to determine the offset timings for two independently controlled staggered refresh cycles for four DRAM devices coupled to the interface circuit, wherein the two independently controlled staggered refresh cycles are staggered by an amount of time equal to approximately half a single refresh cycle associated with the refresh command received from the memory controller, and wherein each of the two independently controlled staggered refresh cycles refreshes a DRAM device in the first group and a DRAM device in the second group.

8. The memory module of claim 1, wherein the calculation unit is configured to determine the offset timings for four independently controlled staggered refresh cycles for eight DRAM devices coupled to the interface circuit, wherein the four independently controlled staggered refresh cycles are staggered by an amount of time equal to approximately a quarter of a single refresh cycle associated with the refresh command received from the memory controller, and wherein each of the four independently controlled staggered refresh cycles refreshes a DRAM device in the first group and a DRAM device in the second group.

9. The memory module of claim 1, wherein the calculation unit is configured to determine the offset timings for eight independently controlled staggered refresh cycles for sixteen DRAM devices coupled to the interface circuit, wherein the eight independently controlled staggered refresh cycles are staggered by an amount of time equal to approximately an eighth of a single refresh cycle associated with the refresh command received from the memory controller and wherein each of the eight independently controlled staggered refresh cycles refreshes a DRAM device in the first group and a DRAM device in the second.

10. The memory module of claim 1, wherein the calculation unit is configured to dynamically determine, at a time subsequent to applying power to the dynamic random access memory devices, the offset timings for the independently controlled staggered refresh cycles that minimize instantaneous power supply load.

11. The memory module of claim 1, wherein the interface circuit further comprises a memory address signal interface, a memory control signal interface, a memory clock signal interface, and a memory data signal interface.

12. The memory module of claim 1, wherein each of the independently controlled staggered refresh cycles is transmitted to exactly two DRAM devices in a group.

13. The memory module of claim 12, wherein the interface circuit is integrated within one of the first group or second group.

14. The memory module of claim 13, wherein the interface circuit comprises an intelligent buffer chip.

15. The memory module of claim 14, wherein the memory module is a dual in-line memory module.

16. The memory module of claim 1, wherein the independently controlled staggered refresh cycles or the scheduling are performed asynchronously.

17. The memory module of claim 16, wherein the memory module is a dual in-line memory module.

18. The memory module of claim 1, wherein a time difference between the timings of each of the N independently controlled staggered refresh cycles differs for each of the independently controlled staggered refresh cycles.

19. A memory module comprising:

2*N dynamic random access memory (DRAM) devices each having a capacity of M, wherein the 2*N DRAM devices comprise;

a first group of N DRAM devices; and

a second group of N DRAM devices, wherein each of the N DRAM devices in the first group shares a distinct refresh control signal with a respective DRAM device in the second group; and

an interface circuit comprising;

emulation logic configured to emulate an interface protocol of two emulated DRAM devices each having a capacity of N*M, wherein a first of the two emulated DRAM devices includes the N DRAM devices from the first group, and a second of the two emulated DRAM devices includes the N DRAM devices from the second group;

a calculation unit configured to determine offset timings for N independently controlled staggered refresh cycles, wherein exactly one DRAM device from the first group and one DRAM device from the second group are refreshed in each of the independently controlled staggered refresh cycles, the offset timings providing timings of each of the independently controlled staggered refresh cycles; and

a scheduler configured to order independently controlled staggered refresh commands directed to the 2*N DRAM devices based on the offset timings determined by the calculation unit.

20. The memory module of claim 19, wherein the interface circuit further comprises:

a measurement unit configured to perform analog signal measurements and to determine a configuration of DRAM devices;

wherein the calculation unit is configured to determine the independently controlled staggered refresh cycles based on measurements received from the measurement unit and the refresh command received from the memory controller.

21. The memory module of claim 19, wherein the calculation unit is configured to dynamically determine, at a time subsequent to applying power to the dynamic random access memory devices, the offset timings for the independently controlled staggered refresh cycles that minimize instantaneous power supply load.

22. A sub-system comprising:

a printed circuit board;

a memory module comprising;

2*N dynamic random access memory (DRAM) devices each having a capacity of M, wherein the 2*N DRAM devices comprise;

a first group of N DRAM devices; and

a second group of N DRAM devices, wherein each of the N DRAM devices in the first group shares a distinct refresh control signal with a respective DRAM device in the second group; and

an interface circuit comprising;

emulation logic configured to emulate an interface protocol of two emulated DRAM devices each having a capacity of N*M, wherein a first of the two emulated DRAM devices includes the N DRAM devices from the first group, and a second of the two emulated DRAM devices includes the N DRAM devices from the second group;

a calculation unit configured to determine offset timings for N independently controlled staggered refresh cycles, wherein exactly one DRAM device from the first group and one DRAM device from the second group are refreshed in each of the independently controlled staggered refresh cycles, the offset timings providing timings of each of the independently controlled staggered refresh cycles; and

a scheduler configured to order independently controlled staggered refresh commands directed to the 2*N DRAM devices based on the offset timings determined by the calculation unit,

wherein the memory module and the interface circuit are mounted to the printed circuit board, and the memory module is electrically coupled to the interface circuit.

23. The sub-system of claim 22, wherein the interface circuit further comprises:

a measurement unit configured to perform analog signal measurements and to determine a configuration of DRAM devices;

wherein the calculation unit is configured to determine the independently controlled staggered refresh cycles based on measurements received from the measurement unit and the refresh command received from the memory controller.

24. The sub-system of claim 22, wherein the calculation unit is configured to dynamically determine, at a time subsequent to applying power to the dynamic random access memory devices, the offset timings for the independently controlled staggered refresh cycles that minimize instantaneous power supply load.