Distributed multi-core memory initialization

• US 8,566,570 B2
• Filed: 10/10/2012
• Issued: 10/22/2013
• Est. Priority Date: 11/24/2009
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Housty, Oswin E.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US13/648,648
• Publication Number:
  US 20130042096A1
• Time in Patent Office: 377 Days
• Field of Search: 713/1, 713/2, 709/208, 709/213, 711/104, 711/114, 711/147, 711/170, 712/23, 712/28, 712/32, 718/102
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Claims

1. A method for causing a plurality of processing nodes to perform a boot process comprising a memory initialization task, comprising:

dividing a memory initialization task into a plurality of memory initialization sub-tasks;

distributing the plurality of memory initialization sub-tasks amongst the plurality of processing nodes so that each memory initialization sub-task has a corresponding processing node by assigning one of the plurality of processing nodes a memory initialization sub-task of reading a serial presence detect (SPD) value from a DIMM memory, and assigning another of the plurality of processing nodes a memory initialization sub-task of executing complex initialization tasks that do not depend on the SPD value;

receiving sub-task results from the plurality of processing nodes; and

combining sub-task results from the plurality of processing nodes.

2. The method of claim 1, further comprising initializing communication links between the plurality of processing nodes prior to distributing the plurality of memory initialization sub-tasks.

3. The method of claim 1, further comprising scheduling the respective memory initialization sub-task for execution at the respective processing node.

4. The method of claim 1, wherein each memory initialization sub-task includes a software routine.

5. The method of claim 1, wherein a first memory initialization sub-task of the plurality of memory initialization sub-tasks is distributed to a first processing node of the plurality of processing nodes, wherein a second memory initialization sub-task of the plurality of memory initialization sub-tasks is distributed to a second processing node of the plurality of processing nodes, and wherein the first memory initialization sub-task and the second memory initialization sub-task of the plurality of memory initialization sub-tasks are executed in parallel.

6. A non-transitory computer readable storage medium storing at least one program configured for execution by at least one processor of a computer system, the at least one program comprising instructions to:

divide a memory initialization task into a plurality of memory initialization sub-tasks;

distribute the plurality of memory initialization sub-tasks amongst the plurality of processing nodes so that each memory initialization sub-task has a corresponding processing node by assigning one of the plurality of processing nodes a memory initialization sub-task of reading a serial presence detect (SPD) value from a DIMM memory, and assigning another of the plurality of processing nodes a memory initialization sub-task of executing complex initialization tasks that do not depend on the SPD value;

receive sub-task results from the plurality of processing nodes; and

combine sub-task results from the plurality of processing nodes.

7. The non-transitory computer readable storage medium of claim 6, wherein the at least one program comprises instructions to initialize communication links between the plurality of processing nodes prior to distributing the plurality of memory initialization sub-tasks.

8. The non-transitory computer readable storage medium of claim 6, wherein the instructions comprise instructions to schedule the respective memory initialization sub-task for execution at the respective processing node.

9. The non-transitory computer readable storage medium of claim 6, wherein each memory initialization sub-task includes a software routine.

10. The non-transitory computer readable storage medium of claim 6, wherein a first memory initialization sub-task of the plurality of memory initialization sub-tasks is distributed to a first processing node of the plurality of processing nodes, wherein a second memory initialization sub-task of the plurality of memory initialization sub-tasks is distributed to a second processing node of the plurality of processing nodes, and wherein the first memory initialization sub-task and the second memory initialization sub-task of the plurality of memory initialization sub-tasks are executed in parallel.

11. A method for causing a plurality of processing nodes to perform a boot process comprising a memory initialization task, comprising:

receiving a directed interrupt for a memory initialization sub-task from a processing node which generates the directed interrupt by writing one or more values to one or more registers, the memory initialization sub-task being one of a plurality of memory initialization sub-tasks that were generated by the processing node by dividing a memory initialization task;

obtaining information from a memory array while executing the memory initialization sub-task; and

returning the results of the memory initialization sub-task to the processing node.

12. The method of claim 11, wherein the one or more values comprises:

a node identifier that identifies a target of the directed interrupt; and

a vector that identifies a series of instructions that comprise the memory initialization sub-task.

13. The method of claim 11, wherein receiving the memory initialization sub-task comprises receiving a memory initialization sub-task of reading a serial presence detect (SPD) value from a DIMM memory.

14. The method of claim 11, wherein receiving the memory initialization sub-task comprises receiving a memory initialization sub-task of executing complex initialization tasks that do not require reading a serial presence detect (SPD) value from a DIMM memory.

15. A non-transitory computer readable storage medium storing at least one program configured for execution by at least one processor of a computer system, the at least one program comprising instructions to:

receive a directed interrupt for a memory initialization sub-task from a processing node which generates the directed interrupt by writing one or more values to one or more registers, the memory initialization sub-task being one of a plurality of memory initialization sub-tasks that were generated by the processing node by dividing a memory initialization task;

obtain information from a memory array while executing the memory initialization sub-task; and

return the results of the memory initialization sub-task to the processing node.

16. The non-transitory computer readable storage medium of claim 15, wherein the one or more values comprise:

a node identifier that identifies a target of the directed interrupt; and

a vector that identifies a series of instructions that comprise the memory initialization sub-task.