Debug state machine and processor including the same
First Claim
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1. An integrated circuit (IC) comprising:
- a module configured to receive debug triggers and initiate a programmed action on a condition that a corresponding debug trigger or a sequence of debug triggers occurs, wherein the programmed action is one of a main action that feeds back to the module and a pre-selected action that is pipelined.
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Abstract
A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.
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20 Claims
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1. An integrated circuit (IC) comprising:
a module configured to receive debug triggers and initiate a programmed action on a condition that a corresponding debug trigger or a sequence of debug triggers occurs, wherein the programmed action is one of a main action that feeds back to the module and a pre-selected action that is pipelined. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of debugging an integrated circuit (IC), the method comprising:
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receiving debug triggers; and initiating a programmed action on a condition that a corresponding debug trigger or a sequence of debug triggers occurs, wherein the programmed action is one of a main action that feeds back to the module and a pre-selected action that is pipelined. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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- 19. A non-transitory computer-readable storage medium storing a code for describing a structure and/or a behavior of a module configured to receive debug triggers and initiate a programmed action on a condition that a corresponding debug trigger or a sequence of debug triggers occurs, wherein the programmed action is one of a main action that feeds back to the module and a pre-selected action that is pipelined.
Specification