Configurable accelerated post-write read to manage errors
First Claim
1. A method of operating a memory system including a non-volatile memory circuit formed of one or more blocks of non-volatile memory cells, the block being a minimum erase unit, where each of the blocks includes one or more groups of memory cells that can be operated in parallel, the method comprising:
- for each of the blocks, maintaining by the memory system of an experience count indicative of the number of erase-program cycles that the corresponding block has experienced;
maintaining by the memory system of a file wherein, for at least first and second non-overlapping ranges of experience counts, a corresponding first and second sample of data in a group of previously programmed memory cells is to be selected for a post-write process, wherein the file is configurable so that the first and second samples can be configured independently;
programming multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC;
subsequent to said programming, selecting by the memory system of a sample of the data programmed in the first group of memory cells from said multiple subsets of data programmed into the first group, wherein the selecting of a sample includes;
determining whether the corresponding experience count for the first group of memory cells corresponds to one of the first or the second non-overlapping ranges of experience counts; and
selecting a sample based on the sample corresponding to the determined experience count in the file;
reading the selected sample;
checking the selected sample as read to determine an amount of error therein, andreprogramming said multiple subsets of data into a second group of memory cells whenever the amount of error determined from the selected sample is more than a predetermined number of error bits.
2 Assignments
0 Petitions
Accused Products
Abstract
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC, where the sample selected depends on the count of erase-program cycles that a block has experienced, where different count ranges can use different samples.
-
Citations
32 Claims
-
1. A method of operating a memory system including a non-volatile memory circuit formed of one or more blocks of non-volatile memory cells, the block being a minimum erase unit, where each of the blocks includes one or more groups of memory cells that can be operated in parallel, the method comprising:
-
for each of the blocks, maintaining by the memory system of an experience count indicative of the number of erase-program cycles that the corresponding block has experienced; maintaining by the memory system of a file wherein, for at least first and second non-overlapping ranges of experience counts, a corresponding first and second sample of data in a group of previously programmed memory cells is to be selected for a post-write process, wherein the file is configurable so that the first and second samples can be configured independently; programming multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC; subsequent to said programming, selecting by the memory system of a sample of the data programmed in the first group of memory cells from said multiple subsets of data programmed into the first group, wherein the selecting of a sample includes; determining whether the corresponding experience count for the first group of memory cells corresponds to one of the first or the second non-overlapping ranges of experience counts; and selecting a sample based on the sample corresponding to the determined experience count in the file; reading the selected sample; checking the selected sample as read to determine an amount of error therein, and reprogramming said multiple subsets of data into a second group of memory cells whenever the amount of error determined from the selected sample is more than a predetermined number of error bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A non-volatile memory system comprising:
-
a memory circuit formed of an array of one or more blocks of non-volatile memory cells, the block being a minimum erase unit, where each of the blocks includes one or more groups of memory cells; programming circuitry connectable to the memory array to program multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC; logic circuitry, where the logic circuitry is configured to perform processes including; for each of the blocks, maintaining an experience count indicative of the number of erase-program cycles that the corresponding block has experienced; maintaining of a file wherein, for at least first and second non-overlapping ranges of experience counts, a corresponding first and second sample of data in a group of previously programmed memory cells is to be selected for a post-write process, wherein the file is configurable so that the first and second samples can be configured independently; and selecting a sample of the data programmed in the first group of memory cells, the sample being selected from a subset of data said multiple subsets of data programmed into the first group, where selecting a sample includes determining whether the corresponding experience count for the first group of memory cells corresponds to one of the first or the second non-overlapping ranges of experience counts; and selecting a sample by the logic circuitry based on the sample corresponding to the determined experience count in the file; reading circuitry connectable to the memory array to read the selected sample; and ECC decoding circuitry connectable to the read circuitry to check errors in the selected sample, wherein the programming circuitry is further connectable to the memory to reprogram said multiple subsets of data into a second group of memory cells whenever the errors checked from the selected sample is more than a predetermined number of error bits. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
Specification