Selective checkbit modification for error correction

• US 8,566,672 B2
• Filed: 03/22/2011
• Issued: 10/22/2013
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Circello, Joseph C.
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US13/053,962
• Publication Number:
  US 20120246542A1
• Time in Patent Office: 945 Days
• Field of Search: 714/768, 714/773
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.

Claims

1. In a data processing device comprising a processor unit coupled to a memory, a method comprising:

receiving a memory access request comprising a memory address;

determining error correction code (ECC) checkbits based on the memory access request;

selectively inverting a first checkbit of the ECC checkbits based on the memory address.

2. The method of claim 1, wherein selectively inverting the first checkbit comprises:

inverting the first checkbit in response to determining the memory address matches one of a set of predetermined address values.

3. The method of claim 1, wherein determining the ECC checkbits comprises determining the ECC checkbits based on the memory address.

4. The method of claim 1, wherein the memory access request is associated with a data value, and further comprising determining the ECC checkbits based on the memory address and the data value.

5. The method of claim 1, wherein the memory access request is a read operation.

6. The method of claim 1, wherein the memory access request is a write operation.

7. The method of claim 1, wherein selectively inverting the first checkbit based on the memory address comprises:

inverting the first checkbit in response to determining the ECC checkbits match one of a set of predetermined checkbit patterns, the ECC checkbits based on the memory address.

8. A data processing device comprising:

an execution unit to provide a memory address based on a received memory access operation; and

an ECC module coupled to the execution unit, the ECC module to determine error correction code (ECC) checkbits based on the memory address wherein the ECC module selectively inverts a first checkbit of the ECC checkbits based on the memory address.

9. The data processing device of claim 8, wherein the ECC module is to selectively invert the first checkbit in response to determining the ECC checkbits match a predetermined data pattern.

10. The data processing device of claim 9, wherein the predetermined data pattern consists of a plurality of asserted data bits.

11. The data processing device of claim 9, wherein the predetermined data pattern consists of a plurality of negated data bits.

12. The data processing device of claim 8, wherein the memory access request is associated with a data value, and wherein the ECC module is to calculate the ECC checkbits based on the memory address and the data value.

13. The data processing device of claim 8, wherein a bit position of the first checkbit in the ECC checkbits is a fixed bit position.

14. The data processing device of claim 8, wherein a bit position of the first checkbit in the ECC checkbits is determined based on the memory address.

15. A device, comprising:

a first error correction module to receive a memory address and to determine first error correction code (ECC) checkbits based on the memory address; and

a pattern detection module coupled to the error correction module and configured to selectively invert a first checkbit of the first ECC checkbits based on the memory address.

16. The device of claim 15, wherein the pattern detection module selectively inverts the first checkbit based on the first ECC checkbits.

17. The device of claim 15 further comprising:

a second error correction module to receive data associated with the memory address and to determine second ECC checkbits based on the data.

18. The data processing device of claim 17, wherein the pattern detection module comprises an output to provide a data pattern based on the memory address, and further comprising:

a first exclusive-or module coupled to the pattern detection module and the first error correction module, the first exclusive-or module to determine third ECC checkbits by combining the data pattern and the first ECC checkbits based on a first exclusive-or operation.

19. The data processing device of claim 18, further comprising a second exclusive-or module coupled to the first exclusive-or module and the second error correction module, the second exclusive-or module to combine the second ECC checkbits and the third ECC checkbits to determine fourth ECC checkbits.

20. The data processing device of claim 19, further comprising a storage array coupled to the second exclusive-or module, the storage array to store the fourth ECC checkbits and the data at a memory location corresponding to the memory address.