Using a phase change memory as a high volume memory

• US 8,566,674 B2
• Filed: 08/11/2009
• Issued: 10/22/2013
• Est. Priority Date: 09/10/2004
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Ovonyx Incorporated (Micron Technology, Inc.)
• Inventors: Parkinson, Ward D.
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US12/538,906
• Publication Number:
  US 20090300467A1
• Time in Patent Office: 1,533 Days
• Field of Search: 714/773, 714/763
• US Class Current: 714/773
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may be incorporated. The error correcting code may be utilized in ways which do not severely negatively impact read access times, in some embodiments.

Claims

1. A non-transitory computer readable medium storing instructions that, if executed, enable a processor-based system to:

detect an incorrect bit read by an operating phase change memory;

correct the bit on its way to be output while deferring writing the corrected bit back to the memory;

detect a memory power cycle; and

repair said incorrect bit, by writing it back memory, using error correcting code during the memory power cycle.

2. The medium of claim 1 further storing instructions that, if executed, enable the processor-based system to correct an incorrect bit by writing back a correct bit.

3. The medium of claim 2 further storing instructions that, if executed, enable the processor-based system to wait until a power cycle to write back a corrected bit.

4. The medium of claim 1 further storing instructions that, if executed, enable the processor-based system to executed error correcting code.

5. The medium of claim 4 further storing instructions that, if executed, enable the processor-based system to identify errors using a Hamming code.