Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program

• US 8,566,762 B2
• Filed: 02/17/2012
• Issued: 10/22/2013
• Est. Priority Date: 03/09/2011
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Morimoto, Takashi, Hashimoto, Takashi
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/637,818
• Publication Number:
  US 20130019214A1
• Time in Patent Office: 613 Days
• Field of Search: 716/102
• US Class Current: 716/102
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A worst-case temperature calculation unit calculates, based on heat value information of each layer of a three-dimensional integrated circuit to be designed and stack structure information of the three-dimensional integrated circuit, a worst-case temperature of a layer during operation that is targeted for logic synthesis. A logic synthesis library selection unit selects a library appropriate for the calculated worst-case temperature. A logic synthesis unit performs logic synthesis on the targeted layer with use of the selected library.

Claims

1. An integrated circuit design device that designs a three-dimensional integrated circuit with use of a standard cell library, the standard cell library being composed of a plurality of libraries that are each appropriate for a different temperature, the integrated circuit design device comprising:

a temperature calculation unit operable to calculate, based on respective heat values and structure information pieces of respective chips forming layers constituting the three-dimensional integrated circuit to be designed, an operating temperature of a chip forming each of one or more target layers targeted for logic synthesis among the layers constituting the three-dimensional integrated circuit;

a standard cell library selection unit operable to, for each of the target layers, select one library among the libraries that is appropriate for an operating temperature that is closet to and higher than the operating temperature of the chip forming the target layer calculated by the temperature calculation unit; and

a logic synthesis unit operable to perform logic synthesis on each of the target layers with use of the library selected by the selection unit.

2. The integrated circuit design device of claim 1, further comprising a heat value calculation unit operable to calculate the respective heat values of the respective chips forming the layers constituting the three-dimensional integrated circuit.

3. The integrated circuit design device of claim 2, wherein

the heat value calculation unit calculates, for each of the respective chips forming the layers constituting the three-dimensional integrated circuit, a toggle rate by analyzing the chip based on an RTL (Register Transfer Level) description of the chip and an operation vector of the chip that is an operation pattern that results in a highest power consumption, and calculates a power consumption of the chip based on the calculated toggle rate to thereby calculate the respective heat values of the respective chips forming the layers constituting the three-dimensional integrated circuit.

4. The integrated circuit design device of claim 2, wherein

the heat value calculation unit calculates, for each of the respective chips forming the layers constituting the three-dimensional integrated circuit, a toggle rate by analyzing the chip based on an RTL (Register Transfer Level) description of the chip and constraint conditions for the logic synthesis, and calculates a power consumption of the chip based on the calculated toggle rate to thereby calculate the respective heat values of the respective chips forming the layers constituting the three-dimensional integrated circuit.

5. The integrated circuit design device of claim 2, wherein

the heat value calculation unit calculates the respective heat values of the respective chips forming the layers constituting the three-dimensional integrated circuit, by, for each of the respective chips, analyzing the chip based on an RTL (Register Transfer Level) description of the chip to calculate a circuit scale of each of modules constituting the chip, and referring to a predetermined heat value table with use of the RTL description, the calculated circuit scale of the module, a circuit type of the module, and a source voltage to be supplied to the module.

6. The integrated circuit design device of claim 1, wherein

with respect to one or more layers among the layers constituting the three-dimensional integrated circuit, the temperature calculation unit acquires, from a data sheet, respective heat values of respective chips forming the one or more layers.

7. The integrated circuit design device of claim 1, wherein

the structure information pieces each indicate a thicknesses of a corresponding one of the respective chips forming the layers constituting the three-dimensional integrated circuit.

8. The integrated circuit design device of claim 1, wherein

the structure information pieces each indicate a value of thermal conductivity of a corresponding one of the respective chips forming the layers constituting the three-dimensional integrated circuit.

9. The integrated circuit design device of claim 1, wherein

with respect to each of the target layers, in the case where two or more layers including the target layer among the layers constituting the three-dimensional integrated circuit are formed by respective chips having the same circuit structure, the standard cell library selection unit makes a comparison between the two or more layers in operating temperature to select a standard library appropriate for the highest operating temperature resulting from the comparison.

10. The integrated circuit design device of claim 1, wherein

the libraries each include a plurality of standard cells that differ in response duration from each other.

11. A method of designing a three-dimensional integrated circuit with use of a standard cell library, the standard cell library being composed of a plurality of libraries that are each appropriate for a different temperature, the method comprising:

using a computer to perform the steps of;

calculating, based on respective heat values and structure information pieces of respective chips forming layers constituting a three-dimensional integrated circuit to be designed, an operating temperature of a chip forming each of one or more target layers targeted for logic synthesis among the layers constituting the three-dimensional integrated circuit;

selecting, for each of the target layers, one library among the libraries that is appropriate for an operating temperature that is closet to and higher than the operating temperature of the chip forming the target layer calculated; and

performing logic synthesis on each of the target layers with use of the library selected.

12. A non-transitory computer-readable recording medium storing a program for causing a computer to perform a process of designing a three-dimensional integrated circuit with use of a standard cell library, the standard cell library being composed of a plurality of libraries that are each appropriate for a different temperature, the process comprising:

calculating, based on respective heat values and structure information pieces of respective chips forming layers constituting a three-dimensional integrated circuit to be designed, an operating temperature of a chip forming each of one or more target layers targeted for logic synthesis among the layers constituting the three-dimensional integrated circuit;

selecting, for each of the target layers, one library among the libraries that is appropriate for an operating temperature that is closet to and higher than the operating temperature of the chip forming the target layer calculated; and

performing logic synthesis on each of the target layers with use of the library selected.