Enhanced analysis of array-based netlists via phase abstraction

• US 8,566,764 B2
• Filed: 04/30/2010
• Issued: 10/22/2013
• Est. Priority Date: 04/30/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Baumgartner, Jason R., Case, Michael L., Mony, Hari, Roessler, Paul J.
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US12/771,404
• Publication Number:
  US 20110271243A1
• Time in Patent Office: 1,271 Days
• Field of Search: 716/106, 716/108, 703/14
• US Class Current: 716/108
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.

Claims

1. A method, in a data processing system, for performing phase abstraction on an integrated circuit design with a memory array, the method comprising:

receiving, by the data processing system, a netlist for an integrated circuit design, wherein the netlist comprises a memory array;

for a given memory array in the netlist, duplicating each write port of the given memory array for a plurality of time values up to an unfold degree to form a plurality of write ports and unfolding each enable pin, address pin, and data pin in each write port within the plurality of write ports;

for the given memory array in the netlist, duplicating each read port of the given memory array for the plurality of time values to form a plurality of read ports and unfolding each enable pin, address pin, and data pin in each read port within the plurality of read ports;

for each data pin of the plurality of read ports, creating a multiplexor structure to form a phase abstracted integrated circuit design, wherein the multiplexor structure selects an output of the data pin based on whether an address of the read port is out-of-bounds, whether the read port is enabled, and whether the memory array is a write-before-read array; and

outputting, by the data processing system, the phase abstracted integrated circuit design.

2. The method of claim 1, further comprising:

responsive to the memory array being a write-before-read array, converting the memory array to a read-before-write array.

3. The method of claim 2, further comprising:

adding a bypass path around the array from write ports to read ports to capture concurrent read and write forwarding.

4. The method of claim 1, further comprising:

adding a set of bypass paths to ensure that proper write data the becomes effective concurrent through unfolding is forwarded to a proper read port.

5. The method of claim 1, wherein the multiplexor structure selects a corresponding data pin of the read port if the address of the read port is out-of-bounds or the read port is disabled;

and

wherein the multiplexor structure selects a corresponding highest priority write data pin if the memory array is a write-before-read array and any write port for a given time value is enabled for an address that matches the address of the read port.

6. The method of claim 1, further comprising:

performing verification on the phase abstracted integrated circuit design to form a phase abstracted trace; and

undoing effects of phase abstraction in the trace to form a new trace.

7. The method of claim 6, wherein undoing the effects of phase abstraction comprises:

for each trace time value in the phase abstracted trace, applying time zero values from the phase abstracted trace to the new trace; and

for each trace time value in the phase abstracted trace, for each phase abstracted time value and for each write port from lower to higher precedence, inject value to the new trace for an actual time value if the write port is enabled for the given time value.

8. The method of claim 7, wherein the actual time value is the trace time value multiplied by the unfold degree plus the abstracted time value plus one if the memory array is a write-before-read array and wherein the actual time value is the trace time value multiplied by the unfold degree plus the phase abstracted time value if the memory array is a read-before-write array.

9. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive, by the computing device, a netlist for an integrated circuit design, wherein the netlist comprises a memory array;

for a given memory array in the netlist, duplicate each write port of the given memory array for a plurality of time values up to an unfold degree to form a plurality of write ports and unfold each enable pin, address pin, and data pin in each write port within the plurality of write ports;

for the given memory array in the netlist, duplicate each read port of the given memory array for the plurality of time values to form a plurality of read ports and unfold each enable pin, address pin, and data pin in each read port within the plurality of read ports;

for each data pin of the plurality of read ports, create a multiplexor structure to form a phase abstracted integrated circuit design, wherein the multiplexor structure selects an output of the data pin based on whether an address of the read port is out-of-bounds, whether the read port is enabled, and whether the memory array is a write-before-read array; and

output, by the computing device, the phase abstracted integrated circuit design.

10. The computer program product of claim 9, wherein the computer readable program further causes the computing device to:

responsive to the memory array being a write-before-read array, converting the memory array to a read-before-write array.

11. The computer program product of claim 10, wherein the computer readable program further causes the computing device to:

adding a bypass path around the array from write ports to read ports to capture concurrent read and write forwarding.

12. The computer program product of claim 9, wherein the computer readable program further causes the computing device to:

adding a set of bypass paths to ensure that proper write data the becomes effective concurrent through unfolding is forwarded to a proper read port.

13. The computer program product of claim 9, wherein the multiplexor structure selects a corresponding data pin of the read port if the address of the read port is out-of-bounds or the read port is disabled;

and

wherein the multiplexor structure selects a corresponding highest priority write data pin if the memory array is a write-before-read array and any write port for a given time value is enabled for an address that matches the address of the read port.

14. The computer program product of claim 9, wherein the computer readable program further causes the computing device to:

performing verification on the phase abstracted integrated circuit design to form a phase abstracted trace; and

undoing effects of phase abstraction in the trace to form a new trace.

15. The computer program product of claim 9, wherein the computer readable program is stored in a computer readable storage medium in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.

16. The computer program product of claim 9, wherein the computer readable program is stored in a computer readable storage medium in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage medium with the remote system.

17. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

receive a netlist for an integrated circuit design, wherein the netlist comprises a memory array;

for a given memory array in the netlist, duplicate each write port of the given memory array for a plurality of time values up to an unfold degree to form a plurality of write ports and unfold each enable pin, address pin, and data pin in each write port within the plurality of write ports;

for the given memory array in the netlist, duplicate each read port of the given memory array for the plurality of time values to form a plurality of read ports-and unfold each enable pin, address pin, and data pin in each read port within the plurality of read ports;

for each data pin of the plurality of read ports, create a multiplexor structure to form a phase abstracted integrated circuit design, wherein the multiplexor structure selects an output of the data pin based on whether an address of the read port is out-of-bounds, whether the read, port is enabled, and whether the memory array is a write-before-read array; and

output the phase abstracted integrated circuit design.

18. The apparatus of claim 17, wherein the instructions further cause the processor to:

responsive to the memory array being a write-before-read array, converting the memory array to a read-before-write array.

19. The apparatus of claim 18, wherein the instructions further cause the processor to:

adding a bypass path around the array from write ports to read ports to capture concurrent read and write forwarding.

20. The apparatus of claim 17, wherein the instructions further cause the processor to:

adding a set of bypass paths to ensure that proper write data the becomes effective concurrent through unfolding is forwarded to a proper read port.