Layout method for soft-error hard electronics, and radiation hardened logic cell

• US 8,566,770 B2
• Filed: 10/19/2011
• Issued: 10/22/2013
• Est. Priority Date: 01/17/2008
• Status: Active Grant

• Current Assignee: Klas Olof Lilja
• Original Assignee: Klas Olof Lilja
• Inventors: Lilja, Klas Olof
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US13/277,135
• Publication Number:
  US 20120185816A1
• Time in Patent Office: 734 Days
• Field of Search: 716/106, 716/111, 716/119, 716/120, 716/132, 716/136, 716/139, 716/55, 326/9, 326/12, 326/14
• US Class Current: 716/119
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H03K 19/0033 Radiation hardening
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Claims

1. A sequential logic or memory cell and layout, comprising two or more latches, each latch having at least one net that stores a voltage state having a value, and at least one net that stores an opposite value, inverse, of the voltage state, comprising:

a. an arrangement of contact areas of each net of each latch, which keep a certain voltage state or its inverse, in such a way that the contact areas of at least 4 of these nets are positioned along one line in the layout, and positioned relative to each other such that two contact areas which are placed next to each other;

i. are part of nets which carry the same voltage state, and for which a single event has an opposite effect on the voltage state of the net to which the contact area belong;

or

ii. are part of different nets, which carry different voltage states, a certain state and its inverse, and for which said single event has the same effect on the voltage of the net.

2. The sequential logic or memory cell and layout of claim 1 wherein at least two of said latches are redundant latches, said cell and layout further comprising:

a. a filtering or voting circuit connected to outputs of redundant nets of the redundant latches, wherein the filtering circuit for two redundant nets of two redundant latches is configured to prevent a data signal to pass unless both redundant nets have the correct data, and for three or more redundant nets of three or more redundant latches, said voting circuit is configured to vote between the states of the redundant nets; and

b. a layout where the strength of the response to the single event has been adjusted such that the total effect, caused by the single event on a primary net of said at least 4 nets, is opposite to the total effect caused by said single event on its redundant counterpart net, such that when said single event affects both said primary net and said redundant counterpart net, one and only one, of these nets can change its state.

3. The sequential logic or memory cell and layout of claim 2 wherein contact areas of a redundant latch of the redundant latches are positioned along said line so that opposing nodes in a primary net or a secondary net of the redundant latch are next to one another or opposing nodes of both the primary net and the secondary net of said redundant latch are next to one another.

4. The sequential logic or memory cell and layout of claim 2 wherein a redundant latch of said redundant latches comprises at least one of:

(i) a first net having a pmos drain or source contact area of a p-type MOSFET transistor and a second net, having the opposite voltage state of the first net, and having a pmos drain or source contact area of a p-type MOSFET transistor and wherein said pmos drain contact areas are next to each other in said arrangement; and

(ii) said first net having an nmos drain contact area of an n-type MOSFET transistor, and said second net having an nmos drain contact area of an n-type MOSFET transistor, and wherein said nmos drain contact areas are next to each other in said arrangement.

5. The sequential logic or memory cell and layout of claim 4 wherein (i) the nmos drain contact area and the pmos drain contact area of the first net are next to each other in said arrangement, and/or (ii) the nmos drain contact area and the pmos drain contact area of the second net are next to each other in said arrangement.

6. The sequential logic or memory cell and layout of claim 1 wherein contact areas of a latch are positioned along said line so that (i) opposing nodes in a first net or a second net of said latch are next to one another or (ii) opposing nodes of the first net of said latch are next to one another or (iii) opposing nodes of the second net of said latch are next to one another.

7. The sequential logic or memory cell and layout of claim 1 wherein said at least two latches form part of (i) a primary net having a dominant node and a non-dominant node comprised of primary net contact areas, and (ii) a redundant net having a dominant node and a non-dominant node comprised of redundant net contact areas, the dominant node having a contact area having an opposing circuit effect to a contact area of the non-dominant node in response to the single event, the dominant node being positioned next to the non-dominant node, the dominant node of the primary net having opposite state to the dominant node of the redundant net, the primary net contact areas and the redundant net contact areas being positioned such that the single event that affects both the primary net and the redundant net also affects both the dominant and the non-dominant nodes in each of the primary net and the redundant net.

8. The sequential logic or memory cell and layout of claim 7 wherein said dominant node of the primary net has a larger contact area or a different contact area position relative to other components of the cell than said non-dominant node.

9. The sequential logic or memory cell and layout of claim 1 wherein a first latch of said latches comprises a first net of said at least 4 nets having an nmos drain or source contact area of an n-type MOSFET transistor and a second net of said at least 4 nets, having the opposite voltage state of the first net, and having an nmos drain or source contact area of an n-type MOSFET transistor and wherein the nmos drain or source contact area of the first net and the nmos drain contact area of the second net are next to each other in said arrangement.

10. The sequential logic or memory cell and layout of claim 9 wherein a contact area which is not connected to any of the nets of said first latch, resides between said nmos drain contact areas.

11. The sequential logic or memory cell and layout of claim 1 wherein a first latch of said latches comprises a first net of said at least 4 nets having a pmos drain or source contact area of a first transistor of a p-type MOSFET transistor and a second net of said at least 4 nets, having the opposite voltage state of the first net, and having a pmos drain or source contact area of a p-type MOSFET transistor and wherein the pmos drain contact area of the first net and the pmos drain contact area of the second net are next to each other in said arrangement.

12. The sequential logic or memory cell and layout of claim 11 wherein a contact area which is not connected to any of the nets of said first latch, resides between said pmos drain contact areas in said arrangement.

13. The sequential logic or memory cell and layout of claim 11 wherein the first net further comprises an nmos drain or source contact area of an n-type MOSFET transistor and wherein the pmos drain contact area of the first net and said nmos drain contact area are next to each other in said arrangement.

14. The sequential logic or memory cell and layout of claim 13 wherein a contact area, which is not connected to any of the said at least 4 nets which are part of said first latch, resides between said nmos drain contact areas in said arrangement.

15. The sequential logic or memory cell and layout of claim 11 wherein the second net further comprises an nmos drain or source contact area of an n-type MOSFET transistor and wherein the pmos drain contact area of the second net and the nmos drain contact area of the second net are next to each other in said arrangement.

16. The sequential logic or memory cell and layout of claim 15 wherein a contact area, which is not connected to any of the said at least 4 nets which are part of said first latch, resides between said nmos drain contact areas in said arrangement.

17. An integrated electronic circuit comprising:

contact areas categorized to identify for which contact areas a single event has opposing effects on the voltage state of nets in the circuit, and to identify for which contact areas a single event has non-opposing effects on the voltage state of the nets in the circuit, wherein the effect on the voltage state of the nets in the circuit due to a single event occurring near each of the contact areas is determined for each of the contact areas in the circuit;

wherein the contact areas are placed in such a way that when a single event has opposing effects on the voltage state of the circuit nets, the opposing first and second contact areas are placed as close to each other as permitted by the circuit and by design rules associated with the circuit;

a first contact area and a second contact area placed with non-opposing effects on the voltage state of the nets in the circuit, said non-opposing effects caused by a single event, wherein the first and second contact areas are non-adjoining, and a third contact area is placed in between the first and second contact areas, wherein said third contact area has an effect on the voltage state of the nets in the circuit opposing those of the first and second contact areas, and wherein the effect of the third contact area on the voltage state of the nets in the circuit is caused by a single event; and

wherein the strength of the effect of a single event on the placed contact areas is selected such that the opposing effects are of substantially equal magnitude, but opposite, in effect on the voltage state of the nets in the circuit.

18. The integrated electronic circuit of claim 17, wherein the circuit has at least two nets carrying the same signal or the signal and its inverse, where each of these nets have at least two contact areas for which a single event has an opposing effect on the voltage state of said two nets, comprising:

a first contact area and a second contact area placed, each from a separate redundant net, for which a single event has the effect of changing the voltage state on the two redundant nets, wherein the first and second contact areas are non-adjoining, and a third contact area placed in between the first and second contact areas, said third contact area having an effect on the voltage state on at least one of the redundant nets, and wherein said effect of the third contact area is caused by a single event and opposes the effects of the first and second contact areas; and

wherein the strength of the effect of a single event on the placed contact areas is selected such that any single event that affects the two redundant nets, at maximum can change the state of one of the nets, but never both nets.

19. The integrated electronic circuit of claim 17, wherein the circuit comprises MOSFET devices, further comprising:

all MOSFET source (S) and drain (D) doping areas, which are not directly connected to the power-nets (VSS, VDD) are designated as the contact areas; and

n-type MOSFET drains or sources, are designated as the contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, low, and the p-type MOSFET drains or sources, are designated as the contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, high.

20. The integrated electronic circuit of claim 19, further comprising:

additional MOSFET devices located between two nets, which at any time, carry opposite voltage states, in such a way that if one of the nets is affected by a single event, such that its voltage state is changed, then the additional MOSFET device turns on, connecting the two nets, and hence ensures that the state of the second net is not changed; and

the sources or drains of the p-type MOSFETs connected in the two nets by additional p-type MOSFETs with their gates connected to the high level power net VDD, and the sources or drains of the n-type MOSFETs are connected in the two nets by additional n-type MOSFETs with their gates connected to the low level power net VSS.