Method of forming a compliant bipolar micro device transfer head with silicon electrodes

• US 8,569,115 B1
• Filed: 07/06/2012
• Issued: 10/29/2013
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/543,680
• Time in Patent Office: 480 Days
• Field of Search: 257/619, 257/623, 257/774, 257/E29.324, 438/130, 438/128, 438/158, 438/250, 438/251, 438/253, 438/254, 438/261, 438/263, 438/276, 438/30, 438/39, 438/396
• US Class Current: 438/130
• CPC Class Codes: B32B 38/18 Handling of layers or the laminate
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H02N 13/00 : Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
• CPC Class Codes: Y10T 156/17 : Surface bonding means and/or assemblymeans with work feeding or handling means

Abstract

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

Claims

1. A method of forming a compliant bipolar transfer head array comprising:

etching a top silicon layer of a silicon-on-insulator stack to form a first array of silicon electrodes electrically connected with a first silicon interconnect, and a second array of silicon electrodes aligned with the first array of silicon electrodes and electrically connected with a second silicon interconnect to form an array of bipolar silicon electrode pairs, each silicon electrode in the first and second arrays of silicon electrodes including an electrode lead and a mesa structure that protrudes above the first and second silicon interconnects;

forming a dielectric layer over the first and second arrays of silicon electrodes; and

etching one or more cavities in the base substrate directly underneath the first and second arrays of silicon electrodes such that each silicon electrode in the first and second arrays of silicon electrodes is deflectable into the one or more cavities.

2. The method of claim 1, wherein etching one or more cavities in the base substrate comprises reactive ion etching with a fluorinated plasma selected from the group consisting of SF₆ and XeF₂.

3. The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a separate cavity in the base substrate directly underneath each bipolar silicon electrode pair.

4. The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a single cavity in the base substrate directly underneath the array of bipolar silicon electrode pairs.

5. The method of claim 4, further comprising etching the single cavity in the base substrate such that it wraps around an end of one of the first and second silicon interconnects.

6. The method of claim 1, wherein etching the top silicon layer of the silicon-on-insulator stack exposes a buried oxide layer.

7. The method of claim 6, further comprising forming a patterned layer over the buried oxide layer and the dielectric layer after forming the dielectric layer over the first and second arrays of silicon electrodes, and etching through the buried oxide layer to expose a portion of the base substrate.

8. The method of claim 7, further comprising etching the one or more cavities in the base substrate directly underneath the first and second arrays of silicon electrodes using the dielectric layer as an etching mask.

9. The method of claim 6, wherein forming the dielectric layer comprises thermal oxidation of the first and second arrays of silicon electrodes.

10. The method of claim 6, further comprising etching an array of joint trenches between the mesa structures of the first and second arrays of silicon electrodes simultaneously with etching the top silicon layer of the silicon-on-insulator stack to form the first and second arrays of silicon electrodes, wherein etching the array of joint trenches exposes the buried oxide layer.

11. The method of claim 10, further comprising forming the dielectric layer within the array of joint trenches and in direct contact with the buried oxide layer simultaneously with forming the dielectric layer over the first and second arrays of silicon electrodes.

12. The method of claim 11, wherein forming the dielectric layer comprises thermal oxidation of the first and second arrays of silicon electrodes.

13. The method of claim 12, further comprising completely filling the array of joint trenches with the dielectric layer to form an array of oxide joints between the first and second arrays of silicon electrodes.

14. The method of claim 6, further comprising etching a first backside via opening through the base substrate directly underneath the first silicon interconnect, and etching a second backside via opening through the base substrate directly underneath the second silicon interconnect.

15. The method of claim 14, further comprising, forming a passivation layer within the first and second backside via openings, wherein forming the passivation layer comprises simultaneously thermally oxidizing the first and second arrays of silicon electrodes and the base substrate within the first and second backside via openings.

16. The method of claim 15, further comprising forming a patterned conductive layer within the first and second via openings to make electrical contact with the first and second silicon interconnects.

17. The method of claim 16, wherein forming the patterned conductive layer comprises depositing the patterned conductive layer through a shadow mask.

18. The method of claim 7, further comprising etching through the dielectric layer to expose a first portion of the first silicon interconnect and a second portion of the second silicon interconnect simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

19. The method of claim 18, further comprising etching a first topside via opening through the exposed first portion of the first silicon interconnect and the buried oxide layer, etching a second topside via opening through the exposed second portion of the second silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the first and second topside via openings to make electrical contact with the first and second silicon interconnects.

20. The method of claim 7, further comprising etching through the dielectric layer to expose each of the mesa structures simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

21. The method of claim 20, further comprising forming a patterned second dielectric layer over each of the mesa structures.

22. The method of claim 21, wherein forming the patterned second dielectric layer comprises blanket depositing the second dielectric layer, and removing a portion of the second dielectric layer.

23. The method of claim 22, wherein blanket depositing the second dielectric layer comprises atomic layer deposition.

24. The method of claim 7, further comprising etching through the dielectric layer to expose a first portion of the first silicon interconnect, a second portion of the second silicon interconnect, and each of the mesa structures simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

25. The method of claim 24, further comprising etching a first topside via opening through the exposed first portion of the first silicon interconnect and the buried oxide layer, etching a second topside via opening through the exposed second portion of the second silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the first and second topside via openings to make electrical contact with the first and second silicon interconnects.

26. The method of claim 25, wherein etching the one or more cavities further comprises using the second dielectric layer formed over each of the mesa structures and the conductive layer formed within the first and second topside via openings as an etching mask.