Semiconductor structure and method of fabrication thereof with mixed metal types

• US 8,569,128 B2
• Filed: 12/03/2010
• Issued: 10/29/2013
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Ranade, Pushkar, Sonkusale, Sachin R.
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US12/960,266
• Publication Number:
  US 20110309450A1
• Time in Patent Office: 1,061 Days
• Field of Search: 257/407, 438/217
• US Class Current: 438/217
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.

Claims

1. A method for forming a semiconductor structure, comprising;

forming first and second PMOS transistor elements and first and second NMOS transistor elements, wherein the first PMOS transistor element and the first NMOS transistor element establish a first CMOS transistor pair, and the second PMOS transistor element and the second NMOS transistor element establish a second CMOS transistor pair, by;

forming a first threshold voltage setting region extending under a gate of the first and second PMOS transistor elements, the first threshold voltage region defining a depletion zone when a voltage to the transistor elements is applied;

forming a second threshold voltage setting region extending under a gate of the first and second NMOS transistor elements, the second threshold voltage region defining a depletion zone when the voltage to the transistor elements is applied;

forming a substantially undoped channel region, disposed above the threshold voltage setting regions and below the gates of each of the first and second PMOS and NMOS transistor elements;

concurrently depositing a first gate metal only on the gate of the first PMOS transistor element of the first CMOS transistor pair and the gate of the second NMOS transistor element of the second CMOS transistor pair; and

concurrently depositing a second gate metal only on the gate of the first NMOS transistor element of the first CMOS transistor pair and the gate of the second PMOS transistor element of the second CMOS transistor pair.

2. The method of claim 1, wherein the second gate metal is a modification of the first gate metal.

3. The method of claim 1, wherein at least one of the first gate metal and the second gate metal has a work function between 100 millivolts from band edge to midgap.

4. The method of claim 1, wherein at least one of the first gate metal and the second gate metal has a work function selected to be between midgap and 300 millivolts from midgap.

5. The method of claim 1, further comprising:

forming the gates of the first and second PMOS transistor elements and the first and second NMOS transistor elements after forming respective source and drain regions.

6. The method of claim 1, further comprising:

forming the gates of the first and second PMOS transistor elements and the first and second NMOS transistor elements prior to forming respective source and drain regions.

7. The method, of claim 1, further comprising:

forming a body tap region for at least one of the first and second PMOS transistor elements and first and second NMOS transistor elements to selectively apply a bias thereto.

8. The method of claim 1, wherein the undoped channel is formed by epitaxial growth of silicon.

9. The method of claim 1, wherein the first NMOS transistor element is formed to operate with a predetermined first leakage, the second NMOS transistor element being formed to operate with a second leakage at least ten times lower than the predetermined first leakage.

10. The method of claim 1, wherein the first NMOS transistor element is formed to operate with a predetermined first leakage, the second NMOS transistor element being formed to operate with a second leakage at least fifty times lower than the predetermined first leakage.