Replacement gate electrode with planar work function material layers

• US 8,569,135 B2
• Filed: 07/20/2011
• Issued: 10/29/2013
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Dechao, Han, Shu-Jen, Wong, Keith Kwong Hon, Yuan, Jun
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): MUNOZ, ANDRES F
• Application Number:
  US13/186,597
• Publication Number:
  US 20130020658A1
• Time in Patent Office: 832 Days
• Field of Search: None
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Claims

1. A method of forming a semiconductor structure comprising:

forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;

forming a gate dielectric layer in said gate cavity;

forming at least one planar work function material portion having a topmost surface that is recessed from a topmost surface of said planarization dielectric layer on said gate dielectric layer in said gate cavity, wherein each of said at least one planar work function material portion is formed by anisotropically depositing a work function metal material layer that provides vertical portions of the work function metal material layer having a lesser thickness than a horizontal portion of the work function metal material layer so that said horizontal portion of said work function metal material layer has a thickness that is at least three times a thickness of said vertical portion of said work function metal material layer, wherein forming the at least one planar work function material portion further includes removing said vertical portions of said work function metal material layer with an isotropic etch so the horizontal portion of the work function metal material layer remains to provide the at least one planar work function material portion; and

filling said gate cavity with a metal layer contacting said at least one planar work function material portion.

2. The method of claim 1, wherein each of said at least one planar work function material portion has a uniform thickness between one inner vertical sidewall of said gate dielectric layer and another inner vertical sidewall of said gate dielectric layer.

3. The method of claim 1, wherein said work function metal material layer is deposited by collimated physical vapor deposition (PVD), radio frequency physical vapor deposition (RFPVD) sputtering, or constant voltage substrate bias.

4. The method of claim 1, wherein said isotropic etch is a wet etch or gas phase etch.

5. The method of claim 1, further comprising:

forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and

planarizing said planarization dielectric layer, wherein a topmost surface of a disposable gate cap dielectric is coplanar with said topmost surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure.

6. The method of claim 1, further comprising planarizing said gate dielectric layer and said metal layer, where a remaining portion of said gate dielectric layer forms a gate dielectric and a remaining portion of said metal layer forms a metal portion, and topmost surfaces of said gate dielectric and said metal portion are coplanar with said topmost surface of said planarization dielectric layer.

7. The method of claim 6, wherein said gate dielectric is formed as a U-shaped gate dielectric including a horizontal gate dielectric portion and a vertical gate dielectric portion, wherein said vertical gate dielectric portion contiguously extends from said horizontal gate dielectric portion to said topmost surface of said planarization dielectric layer.

8. The method of claim 6, wherein said topmost surface of said at least one planar work function material portion is a horizontal surface that extends from one inner sidewall of said gate dielectric to another inner sidewall of said gate dielectric.

9. The method of claim 6, wherein said at least one planar work function material portion comprises a stack of a planar work function material portion and another planar work function material portion, said planar work function material portion comprises a metallic material selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, and said another planar work function material portion comprises another metallic material selected from Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.

10. The method of claim 1, wherein the horizontal portion of said work function metal material layer has a thickness that is at least four times a thickness of said vertical portion of said work function metal material layer.

11. The method of claim 1, wherein the horizontal portion of said work function metal material layer has a thickness that is up to five times a thickness of said vertical portion of said work function metal material layer.

12. A method of forming a semiconductor structure comprising:

forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;

forming a gate dielectric layer in said gate cavity;

forming at least one planar work function material portion having a topmost surface that is recessed from a topmost surface of said planarization dielectric layer on said gate dielectric layer in said gate cavity, wherein each of said at least one planar work function material portion comprises a metallic material selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, wherein each of said at least one planar work function material portion is formed by anisotropically depositing a work function metal material layer that provides vertical portions of the work function metal material layer having a lesser thickness than a horizontal portion of the work function metal material layer, wherein forming the at least one planar work function material portion further includes removing said vertical portions of said work function metal material layer with an isotropic etch so the horizontal portion of the work function metal material layer remains to provide the at least one planar work function material portion; and

filling said gate cavity with a metal layer contacting said at least one planar work function material portion.