Polysilicon resistor formation in a gate-last process

• US 8,569,141 B2
• Filed: 08/31/2011
• Issued: 10/29/2013
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Jyh-Huei, Huang, Chun-Hung
• Primary Examiner(s): Ghyka, Alexander
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US13/222,181
• Publication Number:
  US 20130052789A1
• Time in Patent Office: 790 Days
• Field of Search: 438/382, 257/E21.09
• US Class Current: 438/382
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A method includes forming a polysilicon layer over a substrate, forming a hard mask over the polysilicon layer, and doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant. An etching step is performed to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed. After the etching step, the bottom portion of the doped hard mask region is removed. Electrical connections are formed to connect to a portion of the polysilicon layer in order to form a resistor.

Claims

1. A method comprising:

forming a polysilicon layer over a substrate;

forming a hard mask over the polysilicon layer;

doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant;

performing an etching step to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed;

after the etching step, removing the bottom portion of the doped hard mask region; and

forming electrical connections to connect to a portion of the polysilicon layer in order to form a resistor.

2. The method of claim 1 further comprising implanting the portion of the polysilicon layer to dope a p-type or an n-type impurity in order to form a doped polysilicon region, wherein the step of doping the first portion of the hard mask and the step of implanting the portion of the polysilicon layer are performed using a same patterned photo resist as an implantation mask.

3. The method of claim 1 further comprising implanting a portion of the polysilicon layer to dope a p-type or an n-type impurity in order to form a doped polysilicon region, wherein the step of doping the first portion of the hard mask and the step of implanting the portion of the polysilicon layer are performed using different patterned photo resists as masks, and wherein the different patterned photo resists are patterned using a same lithography mask.

4. The method of claim 1 further comprising removing portions of the polysilicon layer not covered by the first portion of the hard mask to form an opening.

5. The method of claim 4 further comprising, after the step of removing the first portion of the hard mask, filling a gate dielectric and a gate electrode into the opening to form a gate stack of a transistor.

6. The method of claim 1, wherein the step of doping the first portion of the hard mask with the dopant comprises implanting carbon into the first portion of the hard mask.

7. A method comprising:

forming a polysilicon layer over a substrate;

forming a hard mask layer over the polysilicon layer;

forming a photo resist over the hard mask layer and patterning the photo resist;

implanting the polysilicon layer with a first dopant to form a doped polysilicon region in the polysilicon layer;

implanting the hard mask layer with a second dopant to form a doped hard mask region in the hard mask layer, wherein the steps of implanting the polysilicon layer and the hard mask layer are performed using the photo resist as an implantation mask;

etching the hard mask layer, wherein portions of the hard mask layer not doped with the second dopant are substantially fully removed after the step of etching, and wherein the doped hard mask region has at least a bottom portion not removed after the step of etching; and

replacing a portion of the polysilicon layer not covered by the doped hard mask region with a gate stack of a transistor.

8. The method of claim 7, wherein the step of implanting the hard mask layer with the second dopant comprises implanting carbon into the hard mask layer.

9. The method of claim 7, wherein in the step of etching the hard mask layer, both the portions of the hard mask layer not doped with the second dopant and the doped hard mask region are exposed and subject to the etching.

10. The method of claim 7 further comprising:

after the step of replacing the portion of the polysilicon layer with the gate stack, removing the doped hard mask region; and

forming electrical connections to connect to the doped polysilicon region to form a resistor.

11. The method of claim 7 further comprising:

before the step of etching the hard mask layer, forming openings in the hard mask layer and the polysilicon layer, wherein the openings extend into the portions of the hard mask layer not doped with the second dopant;

filling the openings with a dielectric material to form an inter-layer dielectric; and

forming electrical connections through the inter-layer dielectric to connect to the doped polysilicon region, wherein the doped polysilicon region forms a resistor.

12. The method of claim 7, wherein the step of implanting the polysilicon layer with the first dopant comprising implanting boron into the polysilicon layer.

13. The method of claim 7, wherein the doped polysilicon region and the doped hard mask region are formed over and overlapping a shallow-trench isolation (STI) region.

14. A method comprising:

forming a polysilicon layer over a substrate;

forming a first photo resist over the polysilicon layer and patterning the first photo resist;

implanting the polysilicon layer with a first dopant to form a doped polysilicon region in the polysilicon layer, wherein the polysilicon layer is implanted using the first photo resist as a mask;

after the step of implanting the polysilicon layer, forming a hard mask layer over the polysilicon layer;

etching the hard mask layer and the polysilicon layer to form a first opening over a well region in the substrate;

forming a second photo resist into the first opening and over the hard mask layer;

patterning the second photo resist to form a second opening in the second photo resist, wherein the second opening is over and overlapping the doped polysilicon region;

implanting the hard mask layer with a second dopant to form a doped hard mask region in the hard mask layer, wherein the step of implanting the hard mask layer is performed using the second photo resist as an implantation mask;

etching the hard mask layer, wherein portions of the hard mask layer not doped with the second dopant are etched through, and wherein the doped hard mask region has at least a bottom portion not removed; and

replacing a portion of the polysilicon layer with a gate stack of a transistor.

15. The method of claim 14, wherein the step of patterning the first photo resist and the step of patterning the second photo resist are performed using a same lithography mask.

16. The method of claim 14, wherein the step of implanting the hard mask layer with the second dopant comprises implanting carbon into the hard mask layer.

17. The method of claim 14, wherein in the step of etching the hard mask layer, both the portions of the hard mask layer not doped with the second dopant and the doped hard mask region are exposed and subject to the etching.

18. The method of claim 14 further comprising:

after the step of replacing, removing the doped hard mask region; and

forming electrical connections to connect to the doped polysilicon region, wherein the doped polysilicon region forms a resistor.

19. The method of claim 14 further comprising:

before the step of etching the hard mask layer, forming openings in the hard mask layer and the polysilicon layer, wherein the openings extend into the portions of the hard mask layer not doped with the second dopant;

filling the openings with a dielectric material to form an inter-layer dielectric; and

forming electrical connections penetrating through the inter-layer dielectric, wherein the doped polysilicon region are connected to the electrical connections to form a resistor.

20. The method of claim 14, wherein the doped polysilicon region and the doped hard mask region are formed over and overlapping a shallow-trench isolation (STI) region.