Three dimensional integration and methods of through silicon via creation

• US 8,569,154 B2
• Filed: 03/16/2012
• Issued: 10/29/2013
• Est. Priority Date: 01/14/2010
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Kinser, Emily R., Wise, Richard, Yusuff, Hakeem
• Primary Examiner(s): CHOI, CALVIN Y
• Application Number:
  US13/422,415
• Publication Number:
  US 20120190189A1
• Time in Patent Office: 592 Days
• Field of Search: 438/514, 438/524, 438/525, 438/533, 438/618, 438/620, 438/622, 438/627, 438/628, 438/638, 438/639, 438/643, 438/644, 438/652, 438/655, 257/E21.575, 257E21584-E21586
• US Class Current: 438/525
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

Claims

1. A method comprising:

patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, the exposed first planar area aligned vertically with a first conductor embedded in the structure;

etching to the exposed first planar area to form a cavity having a first depth in the structure;

removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer;

forming a doped portion in the sacrificial substrate layer, the doped portion aligned vertically with a second conductor embedded in the structure different from the first conductor;

etching the cavity to increase the depth of the cavity, the first conductor being exposed in response to the etching of the cavity; and

etching the doped portion to expose an underlying planar area, and etching the underlying planar area to increase the planar area and depth of a portion of the cavity, the second conductor being exposed in response to increasing the planar area and depth.

2. The method of claim 1, wherein the structure includes a first wafer and a second wafer.

3. The method of claim 1, wherein the structure includes a first chip and a second chip.

4. The method of claim 1, wherein the portion of exposed sacrificial substrate layer in the structure is doped with ions deposited at an oblique angle.

5. The method of claim 4, wherein the oblique angle is between 95 degrees and 175 degrees.

6. The method of claim 1, wherein the method

further comprises:

removing the photoresist layer, the sacrificial substrate layer, and an optical planarization layer;

forming a dielectric portion in the cavity;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric layer;

filling the cavity with a conductive material; and

removing the excess conductive material by planarization.

7. The method of claim 6, wherein the conductive material is operative to electrically connect the first conductor to the second conductor.