Reducing or eliminating pre-amorphization in transistor manufacture

• US 8,569,156 B1
• Filed: 05/16/2012
• Issued: 10/29/2013
• Est. Priority Date: 05/16/2011
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Scudder, Lance, Ranade, Pushkar, Stager, Charles, Sridharan, Urupattur C., Zhao, Dalong
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US13/473,403
• Time in Patent Office: 531 Days
• Field of Search: 438/308, 438/481, 438/527, 438/530
• US Class Current: 438/527
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Claims

1. A method for forming a NMOS field effect transistor (FET) in a doped well of a substrate, the NMOS FET having a source and a drain, comprising the steps of:

forming an in-situ epitaxial carbon doped silicon layer in the doped well;

implanting dopants to form an NMOS anti-punchthrough layer positioned below the carbon doped silicon layer;

implanting dopants in the carbon doped silicon layer to form an NMOS screen layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain;

annealing using a low thermal budget anneal; and

depositing substantially undoped epitaxial silicon layer on the carbon doped silicon layer.

2. The method of claim 1, wherein the first layer of in-situ epitaxial carbon doped silicon layer is operable to substantially limit diffusion of the NMOS screen layer dopants without using pre-amorphization implants.

3. The method of claim 1, further comprising forming a threshold voltage set layer positioned between the NMOS screen layer and the substantially undoped epitaxial silicon layer.

4. The method of claim 1, wherein depositing the in-situ epitaxial layer of carbon doped silicon comprises depositing a blanket epitaxial carbon doped silicon layer.

5. The method of claim 1, wherein depositing the substantially undoped epitaxial silicon layer comprises depositing a blanket epitaxial silicon layer.

6. The method of claim 1, further comprising depositing a second in-situ epitaxial carbon doped silicon layer above the NMOS screen layer before depositing the substantially undoped epitaxial silicon layer.

7. The method of claim 6, further comprising implanting carbon between the NMOS screen layer and the NMOS anti-punchthrough layer.

8. The method of claim 1, further comprising implanting carbon between the NMOS screen layer and the NMOS anti-punchthrough layer.

9. A method for forming a NMOS FET in a doped well of a substrate, further comprising:

implanting dopants to form a NMOS anti-punchthrough layer;

implanting dopants to form a NMOS screen layer;

depositing an in-situ epitaxial carbon doped silicon layer above the NMOS screen layer;

annealing using low thermal budget anneal; and

depositing a substantially undoped epitaxial silicon layer on the substrate;

wherein the in-situ carbon doped silicon layer is operable to substantially limit diffusion of the NMOS screen layer dopants without using pre-amorphization implants.

10. The method of claim 9, wherein the in-situ carbon doped silicon layer has a thickness of approximately 5 nanometers.

11. The method of claim 9, further comprising implanting carbon between the NMOS screen layer and the NMOS anti-punchthrough layer.

12. The method of claim 9, further comprising forming a threshold voltage set layer positioned between the NMOS screen layer and the intrinsic epitaxial layer.

13. The method of claim 9, wherein depositing the layer of in-situ carbon doped silicon layer comprises depositing a blanket epitaxial carbon doped silicon layer.

14. The method of claim 9, wherein depositing the substantially undoped epitaxial silicon layer comprises depositing a substantially undoped blanket epitaxial silicon layer.

15. A method for forming an integrated circuit device in a substrate, comprising:

forming a PMOS field effect transistor (FET) in a first doped well of the substrate, the PMOS FET having a source and a drain, forming the PMOS FET further comprising;

implanting dopants in the first doped well to form a PMOS anti-punchthrough layer; and

implanting dopants in the first doped well to form a PMOS screen layer above the PMOS anti-punchthrough layer, the PMOS screen layer being positioned laterally between eventual positions of the source and the drain; and

forming a NMOS field effect transistor (FET) in a second doped well of the substrate, the NMOS FET having a source and a drain, forming the NMOS FET further comprising;

implanting dopants in the first doped well to form a NMOS anti-punchthrough layer;

forming an in-situ epitaxial carbon doped silicon layer positioned above the NMOS anti-punchthrough layer, the carbon doped silicon layer being formed as a selective epitaxial layer; and

implanting dopants in the carbon doped silicon layer to form a NMOS screen layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain; and

annealing using a low thermal budget anneal; and

forming a substantially undoped epitaxial silicon layer over the PMOS screen layer and the NMOS screen layer, the epitaxial silicon layer being formed as a blanket epitaxial layer.

16. The method of claim 15, further comprising performing pre-amorphization implants for the PMOS FETs to substantially limit diffusion of the PMOS screen layer dopants.

17. A method for forming an integrated circuit device in a substrate, comprising:

forming a PMOS field effect transistor (FET) in a first doped well of the substrate, the PMOS FET having a source and a drain, forming the PMOS FET further comprising;

implanting dopants in the first doped well to form a PMOS anti-punchthrough layer; and

implanting dopants in the first doped well to form a PMOS screen layer above the PMOS anti-punchthrough layer, the PMOS screen layer being positioned laterally between eventual positions of the source and the drain; and

forming a NMOS field effect transistor (FET) in a second doped well of the substrate, the NMOS FET having a source and a drain, forming the NMOS FET further comprising;

implanting dopants in the first doped well to form a NMOS anti-punchthrough layer;

forming a first layer of carbon doped silicon positioned above the NMOS anti-punchthrough layer, the carbon doped silicon layer being formed as a selective epitaxial layer;

forming a second layer of silicon doped with carbon and NMOS screen layer dopants positioned above the first layer, the second layer being formed as a selective epitaxial layer; and

forming a third layer of carbon doped silicon positioned above the second layer, the third layer being formed as a selective epitaxial layer;

implanting dopants in the carbon doped silicon layer to form a NMOS screen layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain; and

annealing using a low thermal budget anneal; and

forming a substantially undoped epitaxial silicon layer over the PMOS screen layer and the NMOS screen layer, the epitaxial silicon layer being formed as a blanket epitaxial layer.

18. A method for forming an integrated circuit device in a substrate, comprising:

forming a PMOS field effect transistor (FET) in a first doped well of the substrate, the PMOS FET having a source and a drain, forming the PMOS FET further comprising;

implanting dopants in the first doped well to form a PMOS anti-punchthrough layer; and

implanting dopants in the first doped well to form a PMOS screen layer above the PMOS anti-punchthrough layer, the PMOS screen layer being positioned laterally between eventual positions of the source and the drain; and

forming a NMOS field effect transistor (FET) in a second doped well of the substrate, the NMOS FET having a source and a drain, forming the NMOS FET further comprising;

implanting dopants in the first doped well to form a NMOS anti-punchthrough layer; and

forming an in-situ epitaxial silicon layer doped with carbon and NMOS screen layer dopants positioned above the NMOS anti-punchthrough layer, the doped silicon layer being formed as a selective epitaxial layer; and

annealing using a low thermal budget anneal; and

forming a substantially undoped epitaxial silicon layer over the PMOS screen layer and the NMOS screen layer, the epitaxial silicon layer being formed as a blanket epitaxial layer.