Device fabrication

• US 8,569,160 B2
• Filed: 10/31/2012
• Issued: 10/29/2013
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Rinerson, Darrell, Cheung, Robin
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US13/665,603
• Publication Number:
  US 20130059436A1
• Time in Patent Office: 363 Days
• Field of Search: None
• US Class Current: 438/598
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/56 Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Claims

1. A method for device fabrication, comprising:

providing a base wafer as part of a front-end-of-the-line (FEOL) circuitry fabrication process;

forming active circuitry on a plurality of FEOL circuitry die on the base wafer, the FEOL circuitry fabrication process operative to configure each FEOL circuitry die for subsequent electrical coupling with one or more layers of memory to be fabricated directly above each FEOL circuitry die;

forming the one or more layers of memory directly on top of each FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process, the forming including electrically coupling a portion of the active circuitry in each FEOL circuitry die with the one or more layers of memory that are formed directly above each FEOL circuitry die.

2. The method of claim 1, wherein fully depreciated capital assets are used for the FEOL circuitry fabrication process.

3. The method of claim 1, wherein substantially depreciated capital assets are used for the FEOL circuitry fabrication process.

4. The method of claim 1, wherein capital assets having substantially no depreciation are used for the BEOL memory fabrication process.

5. The method of claim 1, wherein the FEOL circuitry fabrication process further includes forming a shield layer on the base wafer operative to protect the base wafer during transportation of the base wafer, and

wherein the BEOL memory fabrication process further includes removing the shield layer prior to the forming the one or more layers of memory.

6. The method of claim 1, wherein the FEOL circuitry fabrication process comprises a trailing edge technology selected to provide a first investment cost that is substantially less in cost than a second investment cost for the BEOL memory fabrication process.

7. The method of claim 1, wherein the FEOL circuitry fabrication process has a first cost per wafer and the BEOL memory fabrication process has a second cost per wafer that is greater than the first cost per wafer and the second cost per wafer is approximately one-half of a total fabrication cost or more.

8. The method of claim 1, wherein at least one of the one or more layers of memory includes a memory array.

9. The method of claim 8, wherein the memory array includes an embedded non-volatile memory.

10. The method of claim 8, wherein the memory array includes non-volatile memory.

11. The method of claim 8, wherein the memory array comprises a two-terminal cross-point array.

12. The method of claim 8, wherein the memory array includes a plurality of memory cells, each memory cell having exactly two terminals.

13. The method of claim 1, wherein at least one of the one or more layers of memory includes at least one embedded non-volatile memory.

14. The method of claim 1, wherein the portion of the active circuitry in each FEOL circuitry die is configured for data operations on the one or more layers of memory that are formed directly above each FEOL circuitry die.

15. The method of claim 1, wherein the FEOL circuitry fabrication process occurs at a first fabrication facility and the BEOL memory fabrication process occur at a second fabrication facility.

16. The method of claim 15 and further comprising:

transporting the base wafer from the first fabrication facility to the second fabrication facility.

17. A method for device fabrication, comprising:

forming a first part of an integrated circuit (IC) at a first fabrication facility, the IC initially comprises a front-end-of-the-line (FEOL) circuitry die formed on a base wafer using a FEOL circuitry fabrication process; and

forming a second part of the IC at a second fabrication facility, the second part comprises one or more layers of memory that are directly fabricated above each FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process,

wherein after the forming of the first part and the second part, the IC comprises a unitary die including a base layer with active circuitry fabricated thereon and the one or more layers of memory in contact with and positioned above the base layer and electrically coupled with at least a portion of the active circuitry.

18. The method of claim 17, wherein fully depreciated capital assets are used for the FEOL circuitry fabrication process.

19. The method of claim 17, wherein substantially depreciated capital assets are used for the FEOL circuitry fabrication process.

20. The method of claim 17, wherein capital assets having substantially no depreciation are used for the BEOL memory fabrication process.

21. The method of claim 17, wherein a first investment cost for the FEOL circuitry fabrication process is substantially less than a second investment cost for the BEOL memory fabrication process.

22. A method for device fabrication, comprising:

forming a first part of an integrated circuit (IC) that initially comprises a front-end-of-the-line (FEOL) circuitry die formed on a base wafer using a FEOL circuitry fabrication process; and

forming a second part of the IC, the second part comprises one or more layers of memory that are directly fabricated above the FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process,

wherein after the forming of the first part and the second part, the IC comprises a unitary die including a base layer having active circuitry fabricated thereon and the one or more layers of memory fabricated directly above and in contact with the base layer and electrically coupled with at least a portion of the active circuitry.

23. The method of claim 22, wherein at least one of the one or more layers of memory includes non-volatile memory.

24. The method of claim 23, wherein the non-volatile memory is configured in a memory array.

25. The method of claim 23, wherein the non-volatile memory includes a plurality of memory cells, each memory cell having exactly two terminals.