Method and structure of wafer level encapsulation of integrated circuits with cavity
First Claim
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1. A method for fabricating an integrated circuit, the method comprising:
- providing a first semiconductor substrate having a first surface region;
forming one or more CMOS integrated circuit (IC) devices provided on a CMOS IC device region overlying the first surface region, the CMOS IC device region having a CMOS surface region;
forming a dielectric layer overlying the CMOS surface region;
forming a sacrificial layer overlying a portion of the dielectric layer;
forming an enclosure layer overlying the sacrificial layer;
removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer;
sealing the void region in a predetermined environment, wherein sealing the void region comprises forming a barrier material overlying at least the void region to hermetically seal the one or more CMOS IC devices;
forming a seal ring encircling the CMOS IC devices, the seal ring being electrically coupled with the barrier material to shield the one or more CMOS IC devices.
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Abstract
The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
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Citations
18 Claims
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1. A method for fabricating an integrated circuit, the method comprising:
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providing a first semiconductor substrate having a first surface region; forming one or more CMOS integrated circuit (IC) devices provided on a CMOS IC device region overlying the first surface region, the CMOS IC device region having a CMOS surface region; forming a dielectric layer overlying the CMOS surface region; forming a sacrificial layer overlying a portion of the dielectric layer; forming an enclosure layer overlying the sacrificial layer; removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer; sealing the void region in a predetermined environment, wherein sealing the void region comprises forming a barrier material overlying at least the void region to hermetically seal the one or more CMOS IC devices; forming a seal ring encircling the CMOS IC devices, the seal ring being electrically coupled with the barrier material to shield the one or more CMOS IC devices. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for forming high quality silicon material for photovoltaic devices, the method comprising:
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providing a semiconductor substrate having a surface region, a first portion and a second portion; forming one or more CMOS integrated circuit (IC) on the first portion of the semiconductor substrate; forming one or more sensitive integrated circuit (IC) modules provided on a second portion of the semiconductor substrate, wherein the one or more sensitive integrated circuit (IC) modules are sensitive to ambient interference and changes; forming a seal ring encircling the one or more sensitive integrated circuit modules; forming one or more dielectric layers overlying the one or more CMOS IC devices and the one or more sensitive IC modules to form a passivation structure overlying the one or more CMOS IC devices and the one or more sensitive IC modules; forming a sacrificial layer overlying a portion of the one or more dielectric layers; forming an enclosure layer overlying the sacrificial layer; removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer; and sealing the void region in a predetermined environment. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification