Storage device comprising semiconductor elements

• US 8,569,753 B2
• Filed: 05/27/2011
• Issued: 10/29/2013
• Est. Priority Date: 06/04/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Ieda, Yoshinori, Imai, Keitaro, Kato, Kiyoshi, Yakubo, Yuto, Hata, Yuki
• Primary Examiner(s): Ingham, John C
• Application Number:
  US13/117,588
• Publication Number:
  US 20110297928A1
• Time in Patent Office: 886 Days
• Field of Search: 257/43, 257/72, 257/E29.296, 257/E21.002, 257/E21.404, 438/104, 438/151, 438/763
• US Class Current: 257/43
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Claims

1. A semiconductor device comprising:

a first memory cell comprising a first transistor and a second transistor, the first transistor and the second transistor overlapping with each other at least partly; and

a second memory cell comprising a third transistor and a fourth transistor, the third transistor and the fourth transistor overlapping with each other at least partly,

wherein each of the first transistor and the third transistor comprises;

a first source region;

a first drain region;

a first channel formation region between the first source region and the first drain region, the first channel formation region comprising a first semiconductor material; and

a first gate electrode over the first channel formation region with a first gate insulating layer interposed between the first gate electrode and the first channel formation region,

wherein each of the second transistor and the fourth transistor comprises;

a second channel formation region comprising a second semiconductor material different from the first semiconductor material;

a source electrode electrically connected to the second channel formation region;

a drain electrode electrically connected to the second channel formation region; and

a second gate electrode over the second channel formation region with a second gate insulating layer interposed between the second gate electrode and the second channel formation region,

wherein one of the first source region and the first drain region is electrically connected to one of the source electrode and the drain electrode via a first conductive layer,

wherein the first conductive layer and the first gate electrode are patterned portions of a same layer, and

wherein the one of source electrode and the drain electrode of the second transistor is electrically connected to the one of source electrode and the drain electrode of the fourth transistor via a wiring.

2. The semiconductor device according to claim 1, wherein the first gate electrode is electrically connected to the other of the source electrode and the drain electrode.

3. The semiconductor device according to claim 1, further comprising a second conductive layer overlapping with the other of the source electrode and the drain electrode, wherein a capacitor comprises the other of the source electrode and the drain electrode, the second gate insulating layer, and the second conductive layer.

4. The semiconductor device according to claim 1, wherein the second channel formation region comprises an oxide semiconductor.

5. A semiconductor device comprising:

a first memory cell comprising a first transistor and a second transistor over the first transistor; and

a second memory cell comprising a third transistor and a fourth transistor over the third transistor,

wherein each of the first transistor and the third transistor comprises;

a first channel formation region on an insulating surface;

an impurity region on the insulating surface; and

a first gate electrode over the first channel formation region with a first gate insulating layer interposed between the first gate electrode and the first channel formation region,

wherein each of the second transistor and the fourth transistor comprises;

an oxide semiconductor layer comprising a second channel formation region; and

a second gate electrode over the second channel formation region with a second gate insulating layer interposed between the second gate electrode and the second channel formation region,

wherein each of the first memory cell and the second memory cell further comprises;

a first electrode electrically connected to the oxide semiconductor layer;

a second electrode electrically connected to the oxide semiconductor layer;

a first conductive layer electrically connected to the impurity region; and

a second conductive layer over the second gate insulating layer, the second conductive layer overlapping with the first electrode,

wherein the first electrode is in contact with a top face of the first gate electrode,

wherein the second electrode is in contact with a top face of the first conductive layer, and

wherein the second electrode of the first memory cell is electrically connected to the second electrode of the second memory cell via a wiring.

6. The semiconductor device according to claim 5, wherein the first conductive layer and the first gate electrode are patterned portions of a same layer.

7. The semiconductor device according to claim 5, wherein a capacitor comprises the first electrode, the second gate insulating layer and the second conductive layer.

8. A semiconductor device comprising:

a first channel formation region on an insulating surface;

an impurity region on the insulating surface;

a first insulating layer over the first channel formation region and the impurity region;

a first gate electrode over the first insulating layer, the first gate electrode overlapping with the first channel formation region;

a first electrode over the first gate electrode, the first electrode being in contact with the first gate electrode;

an oxide semiconductor layer in contact with the first electrode, the oxide semiconductor layer comprising a second channel formation region;

a second electrode in contact with the oxide semiconductor layer;

a first conductive layer below the second electrode, the first conductive layer being in contact with a bottom face of the second electrode;

a second insulating layer over the oxide semiconductor layer, the first electrode and the second electrode;

a second gate electrode over the second insulating layer, the second gate electrode overlapping with the second channel formation region;

a second conductive layer over the second insulating layer, the second conductive layer overlapping with the first electrode;

a third insulating layer over the second gate electrode and the second conductive layer; and

a wiring over the third insulating layer, the wiring is electrically connected to the second electrode.

9. The semiconductor device according to claim 8, wherein the first conductive layer and the first gate electrode are patterned portions of a same layer.

10. The semiconductor device according to claim 8, wherein a capacitor comprises the first electrode, the second insulating layer and the second conductive layer.