Semiconductor device and manufacturing method thereof

• US 8,569,754 B2
• Filed: 10/31/2011
• Issued: 10/29/2013
• Est. Priority Date: 11/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Nonaka, Yusuke, Omata, Takatsugu, Honda, Tatsuya, Miyanaga, Akiharu, Ohara, Hiroki
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/285,385
• Publication Number:
  US 20120112184A1
• Time in Patent Office: 729 Days
• Field of Search: 257/43, 257/E29.296, 257/E29.095, 257/E29.096, 257/57, 257/59, 438/104, 438/603, 438/608, 438/609
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A semiconductor device having a novel structure or a method for manufacturing the semiconductor device is provided. For example, the reliability of a transistor which is driven at high voltage or large current is improved. For improvement of the reliability of the transistor, a buffer layer is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer such that the end portion of the buffer layer is beyond the side surface of the drain electrode layer (or the source electrode layer) when seen in a cross section, whereby the buffer layer can relieve the concentration of electric field. The buffer layer is a single layer or a stacked layer including a plurality of layers, and includes, for example, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Sn—O film containing SiOx, or the like.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer;

a first buffer layer and a second buffer layer in contact with the oxide semiconductor layer;

a source electrode layer and a drain electrode layer overlapping with the oxide semiconductor layer with the first buffer layer and the second buffer layer provided therebetween, respectively;

a gate insulating layer in contact with the oxide semiconductor layer; and

a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween,

wherein the gate electrode layer has a stacked-layer structure,

wherein one layer of the stacked-layer structure, whose surface is in contact with the gate insulating layer, is a first metal oxide containing nitrogen, and

wherein each of the first buffer layer and the second buffer layer is a second metal oxide containing nitrogen.

2. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer extend beyond a side surface of the source electrode layer and a side surface of the drain electrode layer in a channel length direction, respectively.

3. The semiconductor device according to claim 1, wherein light transmittances of the first buffer layer and the second buffer layer are lower than a light transmittance of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the first metal oxide is the same material as the second metal oxide.

5. The semiconductor device according to claim 1, wherein the second metal oxide comprises a material containing at least indium, oxygen, and nitrogen.

6. The semiconductor device according to claim 1, wherein an another layer of the gate electrode layer comprises a material containing aluminum or copper.

7. The semiconductor device according to claim 1, wherein at least part of the oxide semiconductor layer comprises a crystelline region having c-axis alignment in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer comprise polycrystalline.

9. The semiconductor device according to claim 1, wherein the stacked-layer structure includes three layers.

28. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

10. A semiconductor device comprising:

an oxide semiconductor layer;

a first buffer layer and a second buffer layer in contact with the oxide semiconductor layer;

a source electrode layer and a drain electrode layer overlapping with the oxide semiconductor layer with the first buffer layer and the second buffer layer provided therebetween, respectively;

a gate insulating layer in contact with the oxide semiconductor layer; and

a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween,

wherein the gate electrode layer has a stacked-layer structure,

wherein one layer of the stacked-layer structure, whose surface is in contact with the gate insulating layer, is a first metal oxide containing nitrogen,

wherein each of the first buffer layer and the second buffer layer is a second metal oxide containing nitrogen, and

wherein the surface is a top surface.

11. The semiconductor device according to claim 10, wherein the first buffer layer and the second buffer layer extend beyond a side surface of the source electrode layer and a side surface of the drain electrode layer in a channel length direction, respectively.

12. The semiconductor device according to claim 10, wherein light transmittances of the first buffer layer and the second buffer layer are lower than a light transmittance of the oxide semiconductor layer.

13. The semiconductor device according to claim 10, wherein the first metal oxide is the same material as the second metal oxide.

14. The semiconductor device according to claim 10, wherein the second metal oxide comprises a material containing at least indium, oxygen, and nitrogen.

15. The semiconductor device according to claim 10, wherein an another layer of the gate electrode layer comprises a material containing aluminum or copper.

16. The semiconductor device according to claim 10, wherein at least part of the oxide semiconductor layer comprises a crystalline region having c-axis alignment in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

17. The semiconductor device according to claim 10, wherein the first buffer layer and the second buffer layer comprise polycrystalline.

18. The semiconductor device according to claim 10, wherein the stacked-layer structure includes three layers.

29. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

19. A semiconductor device comprising:

an oxide semiconductor layer;

a first buffer layer and a second buffer layer in contact with the oxide semiconductor layer;

a source electrode layer and a drain electrode layer overlapping with the oxide semiconductor layer with the first buffer layer and the second buffer layer provided therebetween, respectively;

a gate insulating layer in contact with the oxide semiconductor layer; and

a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween,

wherein the gate electrode layer has a stacked-layer structure,

wherein one layer of the stacked-layer structure, whose surface is in contact with the gate insulating layer, is a first metal oxide containing nitrogen,

wherein each of the first buffer layer and the second buffer layer is a second metal oxide containing nitrogen,

wherein the surface is a bottom surface.

20. The semiconductor device according to claim 19, wherein the first buffer layer and the second buffer layer extend beyond a side surface of the source electrode layer and a side surface of the drain electrode layer in a channel length direction, respectively.

21. The semiconductor device according to claim 19, wherein light transmittances of the first buffer layer and the second buffer layer are lower than a light transmittance of the oxide semiconductor layer.

22. The semiconductor device according to claim 19, wherein the first metal oxide is the same material as the second metal oxide.

23. The semiconductor device according to claim 19, wherein the second metal oxide comprises a material containing at least indium, oxygen, and nitrogen.

24. The semiconductor device according to claim 19, wherein an another layer of the gate electrode layer comprises a material containing aluminum or copper.

25. The semiconductor device according to claim 19, wherein at least part of the oxide semiconductor layer comprises a crystalline region having c-axis alignment in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

26. The semiconductor device according to claim 19, wherein the first buffer layer and the second buffer layer comprise polycrystalline.

27. The semiconductor device according to claim 19, wherein the stacked-layer structure includes three layers.

30. The semiconductor device according to claim 19, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

31. A semiconductor device comprising:

an oxide semiconductor layer;

a gate electrode layer overlapping with the oxide semiconductor layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode layer,

wherein the gate electrode layer comprises a first layer and a second layer,

wherein the first layer comprises a metal element, oxygen, and nitrogen,

wherein the second layer comprises copper, and

wherein the first layer, the second layer, and the oxide semiconductor layer overlap with one another.

32. The semiconductor device according to claim 31, wherein the metal element is indium.

33. The semiconductor device according to claim 31, wherein at least part of the oxide semiconductor layer comprises a crystalline region having c-axis alignment in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

34. The semiconductor device according to claim 31, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

35. The semiconductor device according to claim 31, wherein the gate electrode layer is provided under the oxide semiconductor layer.

36. A semiconductor device comprising:

an oxide semiconductor layer;

a source electrode layer electrically connected to the oxide semiconductor layer;

a drain electrode layer electrically connected to the oxide semiconductor layer;

a first buffer layer between the oxide semiconductor layer and the source electrode layer;

a second buffer layer between the oxide semiconductor layer and the drain electrode layer;

a gate electrode layer overlapping with the oxide semiconductor layer; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode layer,

wherein each of the first buffer layer and the second buffer layer comprises a metal element, oxygen, and nitrogen, and

wherein the gate electrode layer comprises a metal element, oxygen, and nitrogen.

37. The semiconductor device according to claim 36, wherein the metal element comprised in each of the first buffer layer and the second buffer layer is indium.

38. The semiconductor device according to claim 36, wherein the gate electrode layer comprises:

a first layer comprising a metal element, oxygen, and nitrogen; and

a second layer comprising one of aluminum and copper,

wherein the first layer and the second layer overlap with each other.

39. The semiconductor device according to claim 36, wherein at least part of the oxide semiconductor layer comprises a crystalline region having c-axis alignment in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

40. The semiconductor device according to claim 36, wherein the gate electrode layer is provided under the oxide semiconductor layer.

41. The semiconductor device according to claim 36, wherein the oxide semiconductor layer comprises indium, gallium and zinc.