Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

• US 8,569,842 B2
• Filed: 10/17/2011
• Issued: 10/29/2013
• Est. Priority Date: 01/07/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weis, Rolf, Hirler, Franz, Stecher, Matthias, Willmeroth, Armin, Deboy, Gerald, Feldtkeller, Martin
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): SPALLA, DAVID C
• Application Number:
  US13/275,151
• Publication Number:
  US 20120175635A1
• Time in Patent Office: 743 Days
• Field of Search: 257/339, 257/367
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 : without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H03K 17/06 : Modifications for ensuring a fully conducting state

Abstract

A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Claims

1. A semiconductor device arrangement, comprising:

a first semiconductor device having a load path; and

a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;

wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,

wherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device and receives a drive voltage that corresponds to a voltage across the load path of the first semiconductor device, and

wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors.

2. The semiconductor device arrangement of claim 1, wherein the first semiconductor device comprises a transistor.

3. The semiconductor device arrangement of claim 1, wherein the first semiconductor device comprises a diode.

4. The semiconductor device arrangement of claim 1,

wherein one of the second transistors that has its load path directly connected to the load path of the first semiconductor device has its control terminal connected to a first load terminal of the first semiconductor device;

and

wherein each of the other second transistors has its control terminal connected to a first load terminal of an adjacent second transistor.

5. The semiconductor device arrangement of claim 1, wherein the first semiconductor device and/or at least one of the second transistors is one of a MOSFET, a MISFET, a MESFET, an IGBT, a JFET, a HEMT, a FINFET, a nanotube device.

6. The semiconductor device arrangement of claim 1, wherein the first semiconductor device and/or the second transistors comprise one of the following materials or compositions thereof:

Si, SiO, SiN, Ge, Ga, Al, GaAs, GaN, carbon, In, InP, SiC.

7. The semiconductor device arrangement of claim 3, wherein the diode is implemented as a MOSFET having a floating gate electrode or having a gate electrode connected to a fixed reference potential.

8. The semiconductor device arrangement of claim 2, wherein the first semiconductor device comprises a normally-off transistor.

9. The semiconductor device arrangement of claim 1, wherein the second transistors are normally-on transistors.

10. The semiconductor device arrangement of claim 2, wherein the first semiconductor device comprises one of an n-channel or a p-channel transistor.

11. The semiconductor device arrangement of claim 1, wherein the second transistors are one of n-channel or p-channel transistors.

12. The semiconductor device arrangement of claim 1, wherein the first semiconductor device and the second transistors are implemented in a common semiconductor body.

13. A semiconductor device arrangement, comprising:

a first semiconductor device having a load path; and

a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;

wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,

wherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device,

wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and

wherein the second transistors are implemented as FINFETs, each second transistor comprising;

at least one semiconductor fin;

a source region, a body region and a drain region arranged in the at least one semiconductor fin, wherein the body region is arranged between the source region and the drain region; and

a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

14. The semiconductor device arrangement of claim 13, wherein the source and drain regions are arranged distant in a longitudinal direction of the at least one semiconductor fin.

15. The semiconductor device arrangement of claim 13, wherein the at least one semiconductor fin includes sidewalls and wherein the gate electrode is arranged at least on one of the sidewalls of the semiconductor fin.

16. The semiconductor device arrangement of claim 13, wherein the at least one semiconductor fin is arranged above a substrate.

17. The semiconductor device arrangement of claim 16, wherein the substrate includes at least one semiconductor layer adjoining the body regions of the second transistors.

18. The semiconductor device arrangement of claim 16, wherein the substrate includes a dielectric layer adjoining the body regions of the second transistors.

19. The semiconductor device arrangement of claim 13, wherein the semiconductor fins of two neighboring second transistors are separated by an insulation layer.

20. The semiconductor device arrangement of claim 13, wherein one FINFET further comprises:

a source electrode connected to the source region; and

a semiconductor region doped complementarily to the source region and connected to the source electrode.

21. The semiconductor device arrangement of claim 13, wherein the first semiconductor device comprises a FINFET comprising:

at least one semiconductor fin;

a source region, a body region and a drain region arranged in the at least one semiconductor fin, the body region being arranged between the source region and the drain region; and

a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

22. A semiconductor device arrangement, comprising:

a first semiconductor device having a load path;

a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;

at least one voltage limiting element coupled in parallel with at least one second transistor and/or in parallel to the first semiconductor device;

wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,

wherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device, and

wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors.

23. A circuit arrangement comprising:

a transistor arrangement with a first transistor having a load path and a control terminal and with a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal, wherein the second transistors have their load paths connected in series and connected in series with the load path of the first transistor, wherein one of the second transistors has its control terminal connected to a load terminal of the first transistor, and wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and

a capacitive storage element connected to the load terminal of one of the second transistors.

24. The circuit arrangement of claim 23, further comprising:

a control circuit having an output terminal coupled to the control terminal of the first transistor and having supply terminals,

wherein the capacitive storage element is connected to the supply terminals of the control circuit.

25. The circuit arrangement of claim 24, further comprising:

a load connected in series with the transistor arrangement, a series circuit that includes the transistor arrangement and the load being connected between input terminals that are configured to have an input voltage applied thereto.

26. The circuit arrangement of claim 25, wherein the load comprises:

a transformer with a first winding connected in series with the transistor arrangement and with a second winding inductively coupled with the first winding; and

a rectifier arrangement coupled to the second winding and comprising output terminals configured to provide an output voltage.

27. The circuit arrangement of claim 24, wherein the control circuit is configured to provide a pulse-width modulated drive signal to the first transistor.

28. A semiconductor device, comprising:

a semiconductor substrate;

a source region disposed in the semiconductor substrate;

a gate electrode overlying and insulated from the substrate;

a channel region disposed in the semiconductor substrate beneath the gate electrode and adjacent the source region;

a drift region disposed in the semiconductor substrate adjacent the channel region;

a drain region disposed in the semiconductor substrate and laterally spaced from the source region by the channel region and the drift region; and

a plurality of transistor devices formed in the drift region.

29. The semiconductor device of claim 28, wherein each transistor of the plurality of transistor devices has a control terminal and a load path between a first load terminal and a second load terminal and wherein the transistor devices have their load paths connected in series.

30. The semiconductor device of claim 28, wherein each transistor of the plurality of transistor devices comprises a finFET.