Stacked semiconductor packages and related methods

• US 8,569,885 B2
• Filed: 09/27/2011
• Issued: 10/29/2013
• Est. Priority Date: 10/29/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Weng, Cheng-Yi
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US13/246,408
• Publication Number:
  US 20120104607A1
• Time in Patent Office: 763 Days
• Field of Search: 257/693, 257/737, 257/738, 257/E23.021, 257/E23.069, 257/686, 257/777, 257/E25.006, 257/E25.013, 257/E25.021, 257/E25.027, 257/E23.085, 438/109, 438612-617
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Claims

1. A semiconductor device package, comprising:

a substrate having an upper surface;

a plurality of pads disposed on the substrate upper surface;

a die electrically connected to the substrate;

a solder mask layer disposed on the substrate upper surface and having a plurality of first openings exposing the pads;

an insulation layer disposed on the solder mask layer and including a plurality of second openings, positions of the second openings corresponding to positions of the first openings; and

a plurality of conductive pillars disposed on at least a subset of the pads, wherein at least a portion of the conductive pillars protrudes from the solder mask layer;

wherein a cross-sectional area of each of the first openings is substantially the same as a cross-sectional area of each of the second openings.

2. The semiconductor device package of claim 1, wherein at least a portion of side surfaces of the conductive pillars is covered by the solder mask layer.

3. The semiconductor device package of claim 1, further comprising a molding compound encapsulating the die and at least part of the solder mask layer.

4. The semiconductor device package of claim 1, wherein an upper surface of each pad further comprises a first surface finish layer on which the conductive pillars are disposed.

5. The semiconductor device package of claim 1, further comprising an insulation layer disposed on the solder mask layer, wherein the insulation layer has a plurality of peripheral openings, positions of the peripheral openings corresponding to positions of at least a portion of the openings in the solder mask layer, the conductive pillars being disposed in the peripheral openings.

6. The semiconductor device package of claim 1, wherein the pads comprise a plurality of first pads and a plurality of second pads, the openings comprise a plurality of first openings and a plurality of second openings, the positions of the first openings correspond to those of the first pads such that the first pads are exposed, the positions of the second openings correspond to those of the second pads such that the second pads are exposed, the conductive pillars are disposed on the second pads.

7. The semiconductor device package of claim 5, wherein the insulation layer comprises a photoresist.

8. The semiconductor device package of claim 1, wherein the package is a bottom package, and further comprising a top package stacked on the bottom package and electrically connected to the conductive pillars.

9. The semiconductor device package of claim 8, wherein the top package comprises a plurality of conductive elements that contact the conductive pillars.

10. The semiconductor device package of claim 1, further comprising a package body encapsulating the die where the plurality of conductive pillars are disposed outside a periphery of the package body.

11. A semiconductor device package, comprising:

a substrate having an upper surface;

a plurality of pads disposed on the substrate upper surface;

a die electrically connected to the substrate;

a solder mask layer disposed on the substrate upper surface and having a plurality of first openings exposing the pads;

an insulation layer disposed on the solder mask layer and including a plurality of second openings, positions of the second openings corresponding to positions of the first openings; and

a plurality of conductive pillars disposed on at least a subset of the pads, wherein the conductive pillars have a lesser width than the pads, such that the solder mask layer covers outer edges of upper surfaces of the pads, and further wherein each of the conductive pillars of at least a subset of the conductive pillars has a uniform width along its length.

12. The semiconductor device package of claim 11, wherein the package is a bottom package, and further comprising a top package stacked on the bottom package and electrically connected to the conductive pillars.

13. The semiconductor device package of claim 12, wherein the top package comprises a plurality of conductive elements that contact the conductive pillars.

14. The semiconductor device package of claim 11, further comprising a package body encapasulating the die where the plurality of conductive pillars are disposed outside a periphery of the package body.

15. The semiconductor device package of claim 11, further comprising a molding compound encapsulating the die and at least part of the solder mask layer.

16. The semiconductor device package of claim 11, further comprising an insulation layer disposed on the solder mask layer, wherein the insulation layer has a plurality of peripheral openings, the positions of the peripheral openings correspond to those of a portion of the openings in the solder mask layer, the conductive pillars are disposed in the peripheral openings.

17. A semiconductor device package, comprising:

a substrate having an upper surface;

a plurality of pads disposed on the substrate upper surface;

a die electrically connected to the substrate;

a first solder mask layer disposed on the substrate upper surface and having a plurality of first openings exposing the pads;

a second solder mask layer disposed on the first solder mask layer and including a plurality of second openings, positions of the second openings corresponding to positions of the first openings; and

a plurality of conductive pillars disposed on at least a subset of the pads, wherein a height of at least a portion of the conductive pillars is greater than a height of the solder mask layer;

wherein a diameter of each of the first openings is substantially the same as a diameter of each of the second openings.

18. The semiconductor device package of claim 17, wherein portions of at least some of the conductive pillars are covered by the solder mask layer.

19. The semiconductor device package of claim 17, further comprising a molding compound encapsulating the die and at least part of the solder mask layer.

20. The semiconductor device package of claim 19, wherein the plurality of conductive pillars are disposed outside a periphery of the molding compound.