Device and method for alignment of vertically stacked wafers and die

• US 8,569,899 B2
• Filed: 12/30/2009
• Issued: 10/29/2013
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H., Kleemeier, Walter, Ferreira, Paul, Sampson, Ronald K.
• Primary Examiner(s): Yang, Minchul
• Application Number:
  US12/650,372
• Publication Number:
  US 20110156284A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257/797, 257/71, 257/E23.179
• US Class Current: 257/797
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Claims

1. A wafer stack, comprising:

a first wafer having a first surface and a second surface;

a plurality of first alignment structures formed through the first wafer having a plurality of first transmission columns arranged in a pattern, a first end and a second end of each of the first transmission columns extending from the first surface by a first distance and the second surface by a second distance, respectively, and the first ends and second ends of the first transmission columns being non-overlaying of any portion of the first and second surface of the first wafer, respectively;

a second wafer having a first surface and a second surface, the second surface of the second wafer positioned facing the first surface of the first wafer; and

a plurality of second alignment structures formed through the second wafer having a plurality of second transmission columns arranged in the same pattern as the first transmission columns, a first end and a second end of each of the second transmission columns extending from the first surface by a third distance and the second surface of the second wafer by a fourth distance, respectively, and the first end and second end of the second transmission columns being non-overlaying of any portion of the first and second surface of the second wafer, respectively.

2. The wafer stack of claim 1 wherein the first and second alignment structures are formed in a first and second die region, respectively.

3. The wafer stack of claim 1 wherein the first and second alignment structures are formed between first and second die regions on the first and second wafer, respectively.

4. The wafer stack of claim 1 wherein each of the first ends of the first transmission columns are in optical communication with respective ones of the second ends of the second transmission columns.

5. The wafer stack of claim 1 wherein at least one of the plurality of first alignment structures has a different number of first transmission columns than the other first alignment structures.

6. The wafer stack of claim 1 wherein the pattern of at least one of the plurality of first transmission columns is different from the pattern of the other first transmission columns.

7. The wafer stack of claim 1 wherein the pattern of the plurality of first transmission columns is the same for each plurality of first alignment structures.

8. The wafer stack of claim 1 wherein each of the first and second transmission columns have a constant width through the first and second wafer and the first and second ends of the first and second transmission columns, respectively, that extend from the first and second surfaces of the first and second wafers have the constant width.

9. A device, comprising:

a first die having a first surface and a second surface;

a plurality of first alignment structures formed through the first die having a plurality of first transmission columns arranged in a pattern, a first end and a second end of each of the first transmission columns extending from the first surface by a first distance and the second surface by a second distance, respectively, and the first ends and second ends of the first transmission columns being non-overlaying of any portion the first and second surface of the first wafer, respectively;

a second die having a first surface and a second surface, the second surface of the second die positioned facing the first surface of the first die; and

a plurality of second alignment structures formed through the second die having a plurality of second transmission columns arranged in the same pattern of the first transmission columns, a first end and a second end of each of the second transmission columns extending from the first surface by a third distance and the second surface by a fourth distance, respectively, and the first end and second end of the second transmission columns being non-overlaying of any portion of the first and second surface of the second wafer, respectively.

10. The device of claim 9 wherein each of the first ends of the first transmission columns are in electrical communication with respective ones of the second ends of the second transmission columns.

11. The device of claim 9 wherein each of the first ends of the first transmission columns are in optical communication with respective ones of the second ends of the second transmission columns.

12. The device of claim 9 wherein the first and second transmission columns are formed from a first material.

13. The device of claim 9 wherein one of the first transmission columns of one of the first alignment structures is a first material and another one of the first transmission columns of the first alignment structures a second material that is different from the first material.

14. The device of claim 13 wherein one of the second transmission columns is the second material, the one of the second transmission columns being configured to interact with the one of the first transmission columns that is the first material.

15. The device of claim 13 wherein one of the second transmission columns is the first material, the one of the second transmission columns being configured to interact with the one of the first transmission columns that is the first material.

16. The device of claim 9 wherein one pattern of the first alignment structures has a first number of the first transmission columns and another pattern of the first alignment structures has a second number of first transmission columns.

17. A device, comprising:

a first die having a first surface and a second surface;

a plurality of first capacitive alignment structures arranged in a first pattern and formed on the first die adjacent to the first surface of the first die;

a second die having a first surface and a second surface, the second surface positioned overlying the first surface of the first die; and

a plurality of second capacitive alignment structures arranged in the same first pattern as the first capacitive alignment structures and formed on the second die adjacent to the second surface that overlies the first surface of the first die, the first and second capacitive alignment structures being configured to form first and second plates, respectively, of a plurality of capacitors arranged in the first pattern,

a plurality of third alignment structures arranged in a second pattern formed adjacent to the first surface of the second die;

a third die having a plurality of fourth alignment structures arranged in the second pattern and configured to form a plurality of capacitors with the plurality of third alignment structures, the first pattern of the second alignment structures being different from the second pattern of third alignment structures on the second die.