Programmable LSI

• US 8,570,065 B2
• Filed: 04/03/2012
• Issued: 10/29/2013
• Est. Priority Date: 04/13/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kobayashi, Hidetomo, Endo, Masami, Shionoiri, Yutaka, Dembo, Hiroki, Nishijima, Tatsuji, Ohshima, Kazuaki, Yoneda, Seiichi, Koyama, Jun
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US13/437,961
• Publication Number:
  US 20120268164A1
• Time in Patent Office: 574 Days
• Field of Search: 365/149, 365/185.08, 365/189.11, 365/189.05, 365/185.33, 326 38- 41
• US Class Current: 326/40
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.

Claims

1. A semiconductor device comprising:

a programmable logic circuit comprising;

a configuration memory comprising;

a volatile storage circuit configured to store configuration data while a power source is supplied to the programmable logic circuit; and

a nonvolatile storage circuit configured to store the configuration data while the power source is not supplied to the programmable logic circuit; and

a memory element configured to store the configuration data,

wherein at least part of the configuration data stored in the memory element is input to the configuration memory, and

wherein the memory element comprises a transistor comprising an oxide semiconductor layer comprising a channel formation region, and a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

2. The semiconductor device according to claim 1,

wherein a function of the programmable logic circuit is changed in accordance with the configuration data.

3. The semiconductor device according to claim 1,

wherein the nonvolatile storage circuit comprises a transistor configured to control storing of the configuration data, and

wherein the transistor comprises an oxide semiconductor layer comprising a channel formation region.

4. The semiconductor device according to claim 3, wherein the nonvolatile storage circuit further comprises a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

5. The semiconductor device according to claim 1,

wherein the volatile storage circuit includes two arithmetic circuits, and

wherein an output from one arithmetic circuit is input to the other arithmetic circuit, and an output from the other arithmetic circuit is input to the one arithmetic circuit.

6. A semiconductor device comprising:

a programmable logic circuit comprising logic elements, each of the logic elements comprising;

a configuration memory comprising;

a volatile storage circuit configured to store configuration data; and

a nonvolatile storage circuit configured to store the configuration data; and

a memory element configured to store the configuration data,

wherein at least part of the configuration data stored in the memory element is input to the configuration memory, and

wherein the memory element comprises a transistor comprising an oxide semiconductor layer comprising a channel formation region, and a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

7. The semiconductor device according to claim 6,

wherein a function of the programmable logic circuit is changed by changing an electrical connection between the logic elements in accordance with the configuration data.

8. The semiconductor device according to claim 6,

wherein the nonvolatile storage circuit comprises a transistor configured to control storing of the configuration data, and

wherein the transistor comprises an oxide semiconductor layer comprising a channel formation region.

9. The semiconductor device according to claim 8, wherein the nonvolatile storage circuit further comprises a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

10. The semiconductor device according to claim 6,

wherein the volatile storage circuit includes two arithmetic circuits, and

wherein an output from one arithmetic circuit is input to the other arithmetic circuit, and an output from the other arithmetic circuit is input to the one arithmetic circuit.

11. A semiconductor device comprising:

a programmable logic circuit comprising logic elements, each of the logic elements comprising;

a configuration memory;

a volatile storage circuit configured to store configuration data; and

a nonvolatile storage circuit configured to store the configuration data;

a look-up table configured to perform different arithmetic processing in accordance with the configuration data; and

a selection circuit configured to change an electrical connection between the logic elements in accordance with the configuration data; and

a memory element configured to store the configuration data,

wherein at least part of the configuration data stored in the memory element is input to the configuration memory, and

wherein the memory element comprises a transistor comprising an oxide semiconductor layer comprising a channel formation region, and a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

12. The semiconductor device according to claim 11, wherein each of the logic elements further comprises a register output a signal corresponding to an output signal from the look-up table in synchronization with a clock signal.

13. The semiconductor device according to claim 11,

wherein the nonvolatile storage circuit comprises a transistor configured to control storing of the configuration data, and

wherein the transistor comprises an oxide semiconductor layer comprising a channel formation region.

14. The semiconductor device according to claim 13, wherein the nonvolatile storage circuit further comprises a capacitor, one of a pair of electrodes of the capacitor being electrically connected to a node set in a floating state when the transistor is turned off.

15. The semiconductor device according to claim 11,

wherein the volatile storage circuit includes two arithmetic circuits, and

wherein an output from one arithmetic circuit is input to the other arithmetic circuit, and an output from the other arithmetic circuit is input to the one arithmetic circuit.