PVT-free calibration circuit for TDC resolution in ADPLL
First Claim
1. An all digital phase locked loop (ADPLL), comprising:
- a controllable time-to-digital converter (TDC) configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the variable phase; and
a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase, and to generate a TDC tuning word that adjusts a resolution of the controllable TDC to account for the effect of variations in PVT conditions.
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Abstract
The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.
48 Citations
20 Claims
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1. An all digital phase locked loop (ADPLL), comprising:
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a controllable time-to-digital converter (TDC) configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom; a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the variable phase; and a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase, and to generate a TDC tuning word that adjusts a resolution of the controllable TDC to account for the effect of variations in PVT conditions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An all digital phase locked loop (ADPLL), comprising:
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a controllable time-to-digital converter (TDC) having a plurality of variable delay elements, wherein the controllable TDC is configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom; a phase detector configured to determine a phase error comprising a difference between the variable phase and a reference phase received from a reference phase accumulator; a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the phase error; and a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error, and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to mitigate the effect of the variations in PVT conditions. - View Dependent Claims (14)
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15. A method, comprising:
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providing power to an all digital phase locked loop (APDLL) comprising a controllable time-to-digital converter (TDC) comprising a plurality of variable delay element; operating the controllable TDC to determining a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom; determining an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase; and generating a TDC tuning word that adjusts a resolution of the controllable TDC to mitigate an effect of the variations in PVT conditions. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification