3D integrated circuit stack-wide synchronization circuit

• US 8,570,088 B2
• Filed: 04/25/2013
• Issued: 10/29/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Silberman, Joel A., Wordeman, Matthew R.
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US13/870,279
• Publication Number:
  US 20130234767A1
• Time in Patent Office: 187 Days
• Field of Search: 327/291, 327/293, 327/295
• US Class Current: 327/291
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Claims

1. A stack-wide synchronization circuit for synchronizing an asynchronous signal in each stratum of a 3D chip stack having two or more strata interconnected using at least a first and a second chain of vias, each of the first and the second chain of vias being in a stack-wide broadcast configuration, the stack-wide synchronization circuit comprising, on each of the two or more strata:

a first connection point for receiving the asynchronous signal;

an off-chip receiver having an input and an output, the input connected to the connection point;

an asynchronous-to-synchronous signal converter having an input connected to an output of the off-chip receiver;

a driver having a non-selection input connected an output of the asynchronous-to-synchronous signal converter;

a second connection point, connected to an output of the driver;

an inter-strata receiver having an input connected to the second connection point; and

a latch having an input connected to an output of the inter-strata receiver,

wherein the first connection point is connected to the first chain of vias and the second connection point is connected to the second chain of vias, the drivers are configured such that an output of a single driver on one of the two or more strata is selected at any given time, and wherein the output of the latch on each of the two or more strata provides a stack-wide synchronous signal during a given clock cycle responsive to a receipt of the asynchronous input signal by the first connection point on any of the two or more strata during an immediately preceding clock cycle with respect to the given clock cycle.

2. The stack-wide synchronization circuit of claim 1, wherein the driver on each of the two or more strata is responsive to one or more programming bits that specify the single selected driver.

3. The stack-wide synchronization circuit of claim 1, wherein the driver is a tri-state driver.

4. The stack-wide synchronization circuit of claim 1, wherein the driver is a multiplexer.

5. The stack-wide synchronization circuit of claim 1, further comprising, on each of the two or more strata, an asynchronous input point connected to the first connection point.

6. The stack-wide synchronization circuit of claim 1, wherein the asynchronous input point comprises at least one of input pads and C4 connections.

7. The stack-wide synchronization circuit of claim 1, wherein the asynchronous-to-synchronous signal converter, the driver, and the latch on the same one of the two or more strata are serially connected in a chain having as taps the first chain of vias and the second chain of vias.