Offset-compensated active load and method

• US 8,570,095 B1
• Filed: 05/11/2012
• Issued: 10/29/2013
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Ryat, Marc Henri
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/469,416
• Publication Number:
  US 20130300484A1
• Time in Patent Office: 536 Days
• Field of Search: None
• US Class Current: 327/530
• CPC Class Codes: H03F 2203/45616 the IC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 2203/45681 the LC comprising offset compensating means
• CPC Class Codes: H03F 2203/45726 the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence
• CPC Class Codes: H03F 3/45771 using switching means

Abstract

In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load.

Claims

1. An offset-compensated active load, comprising:

a first transistor having a control electrode and first and second current carrying electrodes;

a second transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the first transistor coupled to the first current carrying electrode of the second transistor;

a first coupling device having a control terminal and first and second terminals, the control terminal coupled for receiving a first control signal, the first terminal coupled to the control electrode of the first transistor and the second terminal coupled to the second current carrying electrode of the first transistor;

a second coupling device having a control terminal and first and second terminals, the control terminal coupled for receiving a second control signal, the first terminal coupled to the control electrode of the second transistor and the second terminal coupled to the second current carrying electrode of the second transistor;

a first charge storage element having first and second terminals, the first terminal coupled to the control terminal of the first transistor and the second terminal switchably coupled to the second current carrying electrode of the first transistor;

a second charge storage element having first and second terminals, the first terminal coupled to the control terminal of the second transistor and the second terminal switchably coupled to the second current carrying electrode of the first transistor.

2. The offset-compensated active load of claim 1, wherein the first and second coupling devices are first and second transistors, respectively.

3. The offset-compensated active load of claim 1, wherein the first and second control signals are substantially the same signal.

4. The offset-compensated active load of claim 1, wherein the second terminals of the first and second charge storage elements are coupled together.

5. The offset-compensated active load of claim 4, further including a third coupling device having a control terminal coupled for receiving a third control signal, a first terminal coupled to the second current carrying electrode of the first transistor, and a second terminal directly coupled to the second terminal of a first charge storage element of the plurality of charge storage elements.

6. The offset-compensated active load of claim 5, further including a fourth coupling device having a control terminal coupled for receiving a fourth control signal, a first terminal coupled for receiving a first source of operating potential, and a second terminal directly coupled to the second terminal of the first coupling device and to the second terminal of the first charge storage element.

7. The offset-compensated active load of claim 6, wherein the first, second, third, and fourth coupling devices comprise transistors.

10. The circuit with offset compensation of claim 4, wherein the first and second charge storage elements are capacitors.

8. An offset-compensated active load, comprising:

a first transistor having a control electrode and first and second current carrying electrodes;

a second transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the first transistor coupled to the first current carrying electrode of the second transistor;

a first coupling device having a control terminal and first and second terminals, the control terminal coupled for receiving a first control signal, the first terminal coupled to the control electrode of the first transistor and the second terminal coupled to the second current carrying electrode of the first transistor;

a second coupling device having a control terminal and first and second terminals, the control terminal coupled for receiving a second control signal, the first terminal coupled to the control electrode of the second transistor and the second terminal coupled to the second current carrying electrode of the second transistor;

a first charge storage element having first and second terminals, the first terminal coupled to the control electrode of the first transistor;

a second charge storage element having first and second terminals, the first terminal coupled to the control electrode of the second transistor;

a third coupling device having a control terminal coupled for receiving a third control signal, a first terminal coupled to the second current carrying electrode of the first transistor, and a second terminal coupled to the second terminal of the first charge storage element;

a fourth coupling device having a control terminal coupled for receiving a fourth control signal, a first terminal coupled for receiving a first source of operating potential, and a second terminal commonly coupled to the second terminal of the first coupling device and to the second terminal of the first charge storage element; and

further including an input stage having an input terminal and first and second output terminals, the first output terminal coupled to the second current carrying electrode of the first transistor and the second output terminal coupled to the second current carrying electrode of the second transistor.

9. The offset-compensated active load of claim 8, wherein the input stage comprises a pair of differentially coupled transistors.

11. A method of operating an active load to compensate for offset in a circuit, comprising:

providing the active load, wherein the active load comprises a first transistor having a gate, a drain, and a source, a second transistor having a gate, a drain, and a source, a first switch having a control terminal and first and second terminals, a second switch having a control terminal and first and second terminals, a third switch having a control terminal and first and second terminals, a first capacitor having first and second terminals, and a second capacitor having first and second terminals, the sources of the first and second transistors coupled together, the gate of the first transistor coupled to the first terminals of the first switch and the first capacitor, the gate of the second transistor coupled to the first terminals of the second switch and the second capacitor, the second terminal of the first switch coupled to the drain of the first transistor and the first terminal of the third switch, the second terminal of the second switch coupled to the drain of the second transistor, and the second terminals of the first and second capacitors coupled together and to the second terminal of the third switch;

generating an offset current in response to coupling input terminals of an input stage together, closing the first and second switches and opening the third switch, wherein the first and second capacitors are electrically decoupled from the drain of the first transistor and the offset current flows towards the active load;

generating an offset compensation voltage in response to the offset current; and

storing the offset compensation voltage in the first and second capacitors.

12. The method of claim 11, wherein generating the offset current includes closing third and fourth end switches.

13. The method of claim 11, wherein generating the offset compensation voltage in response to the offset current further includes using the first and second transistors to generate the offset compensation voltage.

14. The method of claim 11, wherein generating the offset current includes generating a differential offset current and further including using the first and second transistors to generate first and second portions of the offset compensation voltage, respectively, and storing the first portion of the offset compensation voltage in the first capacitor and the second portion of the offset compensation voltage in the second capacitor.

15. A method of compensating for offset in a circuit, comprising:

providing an active load having first and second transistors, first and second switches, and a plurality of charge storage elements, the first and second transistors each having a control electrode and first and second current carrying electrodes and each charge storage element of the plurality of charge storage elements having first and second terminals, the control electrode of the first transistor coupled to the control electrode of the second transistor through the plurality of charge storage elements, wherein the second terminals of first and second charge storage elements of the plurality of charge storage elements are coupled together at a first node;

operating the active load in a first operating mode, wherein in the first operating mode, the control electrode of the first transistor is coupled to the first current carrying electrode of the first transistor at a second node and the control electrode of the second transistor is coupled to the first current carrying electrode of the second transistor at a third node; and

operating the active load in a second operating mode, wherein in the second operating mode, the first node is decoupled from the first current carrying electrode of the first transistor and the control electrode of the second transistor is decoupled from the first current carrying electrode of the second transistor.

16. The method of claim 15, wherein providing the active load having first and second transistors and the plurality of charge storage elements further includes providing a first charge storage element with first and second terminals and a second charge storage element with first and second terminals, the control electrode of the first transistor coupled to the control electrode of the second transistor through the first and second charge storage elements, wherein the control electrode of the first transistor is coupled to the first terminal of the first charge storage element, the control electrode of the second transistor is coupled to the first terminal of the second charge storage element;

and wherein in the second operating mode the first node is coupled to the first current carrying electrode of the first transistor.

17. The method of claim 16, wherein operating the active load in the first operating mode includes closing a first switch coupled between the second node and the control electrode of the first transistor, closing a second switch coupled between the third node and the control electrode of the second transistor, and closing a third switch coupled between the first node and a first source of operating potential.

18. The method of claim 16, wherein operating the active load in the second operating mode includes opening a first switch coupled between the second node and the control electrode of the first transistor, opening a second switch coupled between the third node and the control electrode of the second transistor, opening a third switch coupled between the first node and a first source of operating potential, and closing a fourth switch coupled between the first node and the second node.

19. The method of claim 16, further including injecting a differential current into the active load.

20. The method of claim 19, further including using the differential current to generate an offset compensation signal and storing the offset compensation signal in the first and second charge storage elements.