Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device and television receiver

• US 8,570,453 B2
• Filed: 10/29/2009
• Issued: 10/29/2013
• Est. Priority Date: 02/03/2009
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tsubata, Toshihide
• Primary Examiner(s): Stahl, Mike
• Application Number:
  US13/146,636
• Publication Number:
  US 20110279734A1
• Time in Patent Office: 1,461 Days
• Field of Search: None
• US Class Current: 349/39
• CPC Class Codes: G02F 1/134354 the sub-pixels being capacitively coupled
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G09G 2320/028 by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

With a configuration in which a first pixel electrode (17a) electrically connected to a first transistor (12) and a second pixel electrode (17b) connected to the first pixel electrode (17a) through a capacitance are provided in a single pixel, a storage capacitance wiring (18j) is formed in the same layer with a data signal line (15j), a second transistor (212c) is electrically connected to the storage capacitance wiring (18j) and to the first pixel electrode (17a), and a third transistor (212b) is electrically connected to the storage capacitance wiring (18j) and to the second pixel electrode (17b), a capacitance coupling type active matrix substrate equipped with transistors for discharge suppresses the aperture ratio reduction and load increase on gate bus lines (scan signal lines).

Claims

1. An active matrix substrate comprising:

scan signal lines that extend in a row direction;

data signal lines that extend in a column direction, the scan signal lines and the data signal lines intersecting each other and defining a matrix of pixel regions;

a first transistor connected to a data signal line and a scan signal line in each of the pixel regions;

second and third transistors connected to a same scan signal line that is different from said scan signal line in each of the pixel regions; and

a storage capacitance wiring,

wherein a first pixel electrode electrically connected to said first transistor and a second pixel electrode connected to said first pixel electrode through a capacitance are provided in each of the pixel regions,

wherein said storage capacitance wiring is formed in a same layer with the data signal lines,

wherein said second transistor is electrically connected to said storage capacitance wiring and said first pixel electrode in each of the pixel regions, and

wherein said third transistor is electrically connected to said storage capacitance wiring and said second pixel electrode in each of the pixel region.

2. The active matrix substrate according to claim 1, wherein said first transistor is connected to a current scan signal line, and said second and third transistors are connected to a previous scan signal line.

3. The active matrix substrate according to claim 2, wherein said second and third transistors are provided near an intersecting portion of said previous scan signal line and said storage capacitance wiring.

4. The active matrix substrate according to claim 1, wherein said storage capacitance wiring extends in the column direction.

5. The active matrix substrate according to claim 1, wherein said storage capacitance wiring overlaps said first and second pixel electrodes through an interlayer insulating film that covers channels of respective transistors.

6. The active matrix substrate according to claim 5, further comprising a first capacitance electrode electrically connected to the first pixel electrode, wherein said first capacitance electrode and said second pixel electrode overlap with each other through an insulating layer.

7. The active matrix substrate according to claim 6, wherein said first capacitance electrode is formed in a same layer with the scan signal lines.

8. The active matrix substrate according to claim 7, wherein said first capacitance electrode and said storage capacitance wiring overlap with each other through a gate insulating film.

9. The active matrix substrate according to claim 7, wherein said first pixel electrode, a drain lead-out electrode led out from the drain electrode of the first transistor, and said first capacitance electrode are connected together by a single contact hole.

10. The active matrix substrate according to claim 8, wherein the first capacitance electrode has two edges that are parallel to each other, the storage capacitance wiring has two edges that are parallel to each other, and the both edges of the storage capacitance wiring fall between the edges of the first capacitance electrode when observed in a plan view.

11. The active matrix substrate according to claim 8, wherein the first capacitance electrode has two edges that are parallel to each other, the storage capacitance wiring has two edges that are parallel to each other, and the both edges of the first capacitance electrode fall between the edges of the storage capacitance wiring when observed in a plan view.

12. The active matrix substrate according to claim 1, wherein the first and the second pixel electrodes are arranged in the column direction.

13. The active matrix substrate according to claim 1, wherein the first and the second pixel electrodes are arranged in the row direction.

14. The active matrix substrate according to claim 1, further comprising a third pixel electrode that is electrically connected to the first pixel electrode.

15. The active matrix substrate according to claim 1, further comprising a second capacitance electrode electrically connected to the second pixel electrode, wherein said second capacitance electrode and said first pixel electrode overlap with each other through an insulating layer.

16. The active matrix substrate according to claim 14, further comprising a second capacitance electrode electrically connected to the second pixel electrode, wherein the second capacitance electrode and the third pixel electrode overlap through an insulating layer.

17. The active matrix substrate according to claim 15, wherein a portion of a drain lead-out electrode led out from the drain electrode of the third transistor functions as said second capacitance electrode.

18. The active matrix substrate according to claim 13, wherein, in one of two pixel regions arranged next to each other in the column direction, the first transistor is connected to one of two adjacent data signal lines, and in the other of said two pixel regions, the first transistor is connected to the other of said two data signal lines.

19. The active matrix substrate according to claim 18, wherein the first pixel electrode provided in one of said two pixel regions and the second pixel electrode provided in another pixel region are adjacent to each other in the column direction.

20. The active matrix substrate according to claim 13, wherein said storage capacitance wiring extends in the column direction and overlaps with the first and the second pixel electrodes and a space between them.

21. The active matrix substrate according to claim 20, further comprising first and second capacitance electrodes in a same layer with the scan signal line, wherein said first capacitance electrode connected to the first pixel electrode through a contact hole crosses under the storage capacitance wiring and arrives under the second pixel electrode, while said second capacitance electrode connected to the second pixel electrode through a contact hole crosses under the storage capacitance wiring and arrives under the first pixel electrode.

22. The active matrix substrate according to claim 21, wherein said first and second capacitance electrodes are formed symmetrically with each other with respect to a point or a line.

23. A liquid crystal panel comprising the active matrix substrate according to claim 1.

24. A liquid crystal display unit comprising the liquid crystal panel according to claim 23 and a driver.

25. A liquid crystal display device comprising the liquid crystal display unit according to claim 24 and a light source device.

26. A liquid crystal display device comprising the active matrix substrate according to claim 19, wherein signal potentials of a same polarity are supplied to respective data signal lines during one vertical period.

27. A television receiver comprising the liquid crystal display device according to claim 25 and a tuner section that receives a television broadcasting.