DC-DC converter current sensing

• US 8,571,492 B2
• Filed: 11/04/2011
• Issued: 10/29/2013
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Berchtold, Jean-Christophe, Colles, Joseph Hubert, Jones, David E., Levesque, Chris, Southcombe, William David, Yoder, Scott, Stockert, Terry J.
• Primary Examiner(s): Nguyen, Simon
• Application Number:
  US13/289,134
• Publication Number:
  US 20120049894A1
• Time in Patent Office: 725 Days
• Field of Search: 4551271-1275, 455/343.1, 455/572, 323/207, 323209-211, 323/237, 323282-283, 323/288, 323344-345
• US Class Current: 455/91
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter

Abstract

A sample-and-hold (SAH) current estimating circuit and a first switching power supply are disclosed. The first switching power supply provides a first switching power supply output signal based on a series switching element and a setpoint. The SAH current estimating circuit samples a voltage across the series switching element of the first switching power supply during an ON state of the series switching element and during a ramping signal peak to provide an SAH output signal based on an estimate of an output current of the first switching power supply output signal. The first switching power supply selects the ON state of the series switching element, such that during the ramping signal peak, the series switching element has a series current having a magnitude, which is about equal to a magnitude of the output current of the first switching power supply output signal.

Claims

1. Circuitry comprising:

a sample-and-hold (SAH) current estimating circuit adapted to sample a voltage across a series switching element during an ON state of the series switching element and during a ramping signal peak to provide an SAH output signal based on an estimate of an output current of a first switching power supply output signal; and

a first switching power supply comprising the series switching element and adapted to;

provide the first switching power supply output signal based on the series switching element and a setpoint; and

select the ON state of the series switching element, such that during the ramping signal peak, the series switching element has a series current having a magnitude, which is about equal to a magnitude of the output current.

2. The circuitry of claim 1 wherein the series switching element is a metal-oxide-semiconductor (MOS) device.

3. The circuitry of claim 2 wherein the series switching element is a P-type MOS (PMOS) device.

4. The circuitry of claim 1 wherein the voltage across the series switching element follows the series current in about a proportional manner.

5. The circuitry of claim 4 wherein during the ON state of the series switching element, the series switching element has an ON resistance, which is about equal to a proportionality constant.

6. The circuitry of claim 1 wherein the first switching power supply further comprises a first inductive element having an average first inductive element current and an instantaneous first inductive element current.

7. The circuitry of claim 6 wherein the output current is about equal to the average first inductive element current.

8. The circuitry of claim 6 wherein during the ramping signal peak, the instantaneous first inductive element current is about equal to the average first inductive element current.

9. The circuitry of claim 1 wherein the first switching power supply further comprises a first inductive element having a first inductive element current, such that during the ON state of the series switching element, the series switching element substantially provides the first inductive element current.

10. The circuitry of claim 1 wherein a ramping signal has the ramping signal peak.

11. The circuitry of claim 10 wherein the first switching power supply output signal is further based on a pulse width modulation (PWM) signal, such that the ramping signal is used to create the PWM signal.

12. The circuitry of claim 1 wherein the estimate of the output current is based on an estimate of the series current of the series switching element during the ON state of the series switching element and during the ramping signal peak.

13. The circuitry of claim 1 wherein:

the SAH current estimating circuit is coupled across the series switching element;

one end of the SAH current estimating circuit and the series switching element are adapted to receive a first sample signal; and

an opposite end of the SAH current estimating circuit and the series switching element are adapted to receive a second sample signal.

14. The circuitry of claim 13 wherein:

the SAH current estimating circuit comprises an SAH switching element and an SAH capacitive element;

one end of the SAH capacitive element is coupled to one end of the SAH switching element;

an opposite end of the SAH capacitive element is adapted to receive the first sample signal; and

an opposite end of the SAH switching element is adapted to receive the second sample signal.

15. The circuitry of claim 14 wherein:

at or before the ramping signal peak, the SAH switching element is ON, such that the SAH capacitive element obtains a voltage between the first sample signal and the second sample signal; and

at or slightly after the ramping signal peak, the SAH switching element transitions from ON to OFF to sample a voltage across the series switching element.

16. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

17. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature radio frequency (RF) power amplifier (PA) coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

18. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising a first final stage having a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

19. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) having a first final stage and adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

20. The circuitry of claim 1 further comprising:

a direct current (DC)-DC converter comprising;

the first switching power supply, which functions as a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry.

21. The circuitry of claim 1 further comprising:

multi-mode multi-band radio frequency (RF) power amplification circuitry having at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with at least a first look-up table (LUT);

power amplifier (PA) control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least the first LUT, which is associated with at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

22. A method comprising:

providing a sample-and-hold (SAH) current estimating circuit;

providing a first switching power supply comprising a series switching element;

sampling a voltage across the series switching element during an ON state of the series switching element and during a ramping signal peak to provide an SAH output signal based on an estimate of an output current of a first switching power supply output signal;

providing the first switching power supply output signal based on the series switching element and a setpoint; and

selecting the ON state of the series switching element, such that during the ramping signal peak, the series switching element has a series current having a magnitude, which is about equal to a magnitude of the output current.