Supporting variable sector sizes in flash storage devices

• US 8,572,308 B2
• Filed: 06/25/2009
• Issued: 10/29/2013
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Moshayedi, Mark, Calvert, William, Boorman, Stephen Russell, Haynes, Simon Mark
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Ahmed, Hamdy S
• Application Number:
  US12/492,103
• Publication Number:
  US 20100042901A1
• Time in Patent Office: 1,587 Days
• Field of Search: 714/773, 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A flash storage device comprises a plurality of data blocks, each data block comprising a plurality of data segments, a system memory, and a controller. The controller is configured to cache in the system memory a plurality of data sectors to be written, to write to a first one of the plurality of data segments a first one of the plurality of data sectors, to write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors, and to write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors.

Claims

1. A flash storage device, comprising:

a plurality of data blocks, each data block comprising a plurality of data segments;

a system memory, and

a controller configured to;

cache in the system memory a plurality of data sectors to be written;

write to a first one of the plurality of data segments a first one of the plurality of data sectors;

write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors; and

write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors.

2. The flash storage device according to claim 1, wherein the controller is further configured to:

calculate error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first one of the plurality of data segments;

calculate error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second one of the plurality of data segments; and

write the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second one of the plurality of data segments.

3. The flash storage device according to claim 1, wherein the first and second ones of the plurality of data segments are data segments of a same one of the plurality of data blocks.

4. The flash storage device according to claim 1, wherein the first and second ones of the plurality of data segments are adjacent data segments.

5. The flash storage device according to claim 1, wherein the plurality of data sectors to be written each have a same size of 2ⁿ bits, where n is a positive integer.

6. The flash storage device according to claim 1, wherein the plurality of data sectors to be written each have a same size of other than 2ⁿ bits, where n is a positive integer.

7. The flash storage device according to claim 1, wherein the system memory includes an addressing table correlating, for each of the plurality of data sectors, a logical address thereof with a physical location thereof in the corresponding one of the plurality of data blocks.

8. The flash storage device according to claim 7, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks.

9. The flash storage device according to claim 1, wherein the system memory comprises a random access memory in the controller.

10. The flash storage device according to claim 1, wherein the system memory comprises one or more buffers provided on one or more flash memory chips in which the plurality of data blocks are disposed.

11. A method of writing data to a flash storage device comprising a plurality of data blocks, each data block comprising a plurality of data segments, the method comprising the steps of:

caching in a system memory a plurality of data sectors to be written;

writing a first one of the plurality of data sectors to a first data segment;

writing a first portion of a second one of the plurality of data sectors to the first data segment; and

writing a second portion of the second one of the plurality of data sectors to a second data segment.

12. The method according to claim 11, further comprising the steps of:

calculating error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first data segment;

calculating error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second data segment; and

writing the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second data segment.

13. The method according to claim 11, wherein the first and second ones of the plurality of data segments are data segments of a same data block.

14. The method according to claim 11, wherein the first and second ones of the plurality of data segments are adjacent data segments.

15. The method according to claim 11, wherein the plurality of data sectors to be written each have a same size of 2ⁿ bits, where n is a positive integer.

16. The method according to claim 11, wherein the plurality of data sectors to be written each have a same size of other than 2ⁿ bits, where n is a positive integer.

17. The method according to claim 11, further comprising the step of:

updating an addressing table correlating, for each of the first and second data sectors, a logical address thereof with a physical location thereof in a corresponding one of a plurality of data blocks.

18. The method according to claim 17, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks.

19. The method according to claim 17, wherein the system memory comprises a random access memory.

20. The method according to claim 17, wherein the system memory comprises one or more buffers provided on one or more flash memory chips.

21. A non-transitory machine readable medium carrying one or more sequences of instructions for writing data to a flash storage device comprising a plurality of data blocks, each data block comprising a plurality of data segments, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:

caching in a system memory of the flash storage device a plurality of data sectors to be written;

writing a first one of the plurality of data sectors to a first data segment of the flash storage device;

writing a first portion of a second one of the plurality of data sectors to the first data segment; and

writing a second portion of the second one of the plurality of data sectors to a second data segment of the flash storage device.

22. The non-transitory machine readable medium according to claim 21, wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the steps of:

calculating error correction information corresponding to the first portion of the second one of the plurality of data sectors before writing the first portion to the first data segment;

calculating error correction information corresponding to the second portion of the second one of the plurality of data sectors before writing the second portion to the second data segment; and

writing the error correction information corresponding to the first and second portions of the second one of the plurality of data sectors to the second data segment.

23. The non-transitory machine readable medium according to claim 21, wherein the first and second ones of the plurality of data segments are data segments of a same data block of the flash storage device.

24. The non-transitory machine readable medium according to claim 21, wherein the first and second ones of the plurality of data segments are adjacent data segments.

25. The non-transitory machine readable medium according to claim 21, wherein the plurality of data sectors to be written each have a same size of 2ⁿ bits, where n is a positive integer.

26. The non-transitory machine readable medium according to claim 21, wherein the plurality of data sectors to be written each have a same size of other than 2ⁿ bits, where n is a positive integer.

27. The non-transitory machine readable medium according to claim 21, wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the step of:

updating an addressing table correlating, for each of the first and second data sectors, a logical address thereof with a physical location thereof in a corresponding one of a plurality of data blocks.

28. The non-transitory machine readable medium according to claim 27, wherein the physical location for each of the plurality of data sectors comprises an offset from a first position in the corresponding one of the plurality of data blocks.

29. The non-transitory machine readable medium according to claim 21, wherein the system memory comprises a random access memory.

30. The non-transitory machine readable medium according to claim 21, wherein the system memory comprises one or more buffers provided on one or more flash memory chips.